Intel-GFX Archive on lore.kernel.org
 help / color / mirror / Atom feed
From: Aditya Swarup <aditya.swarup@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Jani Nikula <jani.nikula@intel.com>,
	Lucas De Marchi <lucas.demarchi@intel.com>
Subject: [Intel-gfx] [PATCH 8/9] drm/i915/adl_s: Add display WAs for ADL-S
Date: Wed, 27 Jan 2021 21:30:23 -0800	[thread overview]
Message-ID: <20210128053024.23540-9-aditya.swarup@intel.com> (raw)
In-Reply-To: <20210128053024.23540-1-aditya.swarup@intel.com>

- Extend permanent driver WA Wa_1409767108, Wa_14010685332
  and Wa_14011294188 to adl-s.
- Extend permanent driver WA Wa_1606054188 to adl-s.
- Add Wa_14011765242 for adl-s A0 stepping.

v2:
- Extend Wa_14011765242 to STEP A1.(mdroper)

Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_power.c | 7 ++++---
 drivers/gpu/drm/i915/display/intel_sprite.c        | 4 ++--
 drivers/gpu/drm/i915/i915_drv.h                    | 1 +
 drivers/gpu/drm/i915/intel_device_info.c           | 6 +++++-
 4 files changed, 12 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index cccfd45a67cf..e17b1ca356c3 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -5339,9 +5339,10 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
 	unsigned long abox_mask = INTEL_INFO(dev_priv)->abox_mask;
 	int config, i;
 
-	if (IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
+	if (IS_ALDERLAKE_S(dev_priv) ||
+	    IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
 	    IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_B0))
-		/* Wa_1409767108:tgl,dg1 */
+		/* Wa_1409767108:tgl,dg1,adl-s */
 		table = wa_1409767108_buddy_page_masks;
 	else
 		table = tgl_buddy_page_masks;
@@ -5379,7 +5380,7 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
 
 	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 
-	/* Wa_14011294188:ehl,jsl,tgl,rkl */
+	/* Wa_14011294188:ehl,jsl,tgl,rkl,adl-s */
 	if (INTEL_PCH_TYPE(dev_priv) >= PCH_JSP &&
 	    INTEL_PCH_TYPE(dev_priv) < PCH_DG1)
 		intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D, 0,
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index d216a863d818..ec931a08ff28 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -2373,8 +2373,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
 		return -EINVAL;
 	}
 
-	/* Wa_1606054188:tgl */
-	if (IS_TIGERLAKE(dev_priv) &&
+	/* Wa_1606054188:tgl,adl-s */
+	if ((IS_ALDERLAKE_S(dev_priv) || IS_TIGERLAKE(dev_priv)) &&
 	    plane_state->ckey.flags & I915_SET_COLORKEY_SOURCE &&
 	    intel_format_is_p01x(fb->format->format)) {
 		drm_dbg_kms(&dev_priv->drm,
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9713ab963122..a1fef2176ae0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1559,6 +1559,7 @@ extern const struct i915_rev_steppings kbl_revids[];
 
 enum {
 	STEP_A0,
+	STEP_A1,
 	STEP_A2,
 	STEP_B0,
 	STEP_B1,
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 85d6883745d8..06df1911cc7d 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -250,7 +250,11 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
 	struct intel_runtime_info *runtime = RUNTIME_INFO(dev_priv);
 	enum pipe pipe;
 
-	if (INTEL_GEN(dev_priv) >= 10) {
+	/* Wa_14011765242: adl-s A0 */
+	if (IS_ADLS_DISP_STEPPING(dev_priv, STEP_A0, STEP_A1))
+		for_each_pipe(dev_priv, pipe)
+			runtime->num_scalers[pipe] = 0;
+	else if (INTEL_GEN(dev_priv) >= 10) {
 		for_each_pipe(dev_priv, pipe)
 			runtime->num_scalers[pipe] = 2;
 	} else if (IS_GEN(dev_priv, 9)) {
-- 
2.27.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  parent reply	other threads:[~2021-01-28  5:31 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-28  5:30 [Intel-gfx] [PATCH 0/9] Final set of patches for ADLS enabling Aditya Swarup
2021-01-28  5:30 ` [Intel-gfx] [PATCH 1/9] drm/i915/adl_s: Update PHY_MISC programming Aditya Swarup
2021-01-28  5:30 ` [Intel-gfx] [PATCH 2/9] drm/i915/adl_s: MCHBAR memory info registers are moved Aditya Swarup
2021-01-28  5:30 ` [Intel-gfx] [PATCH 3/9] drm/i915/adl_s: Add power wells Aditya Swarup
2021-01-28  5:30 ` [Intel-gfx] [PATCH 4/9] drm/i915/adl_s: Re-use TGL GuC/HuC firmware Aditya Swarup
2021-01-28  5:30 ` [Intel-gfx] [PATCH 5/9] drm/i915/display: Add HAS_D12_PLANE_MINIMIZATION Aditya Swarup
2021-01-28  5:30 ` [Intel-gfx] [PATCH 6/9] drm/i915/adl_s: Load DMC Aditya Swarup
2021-01-28  5:30 ` [Intel-gfx] [PATCH 7/9] drm/i915/adl_s: Update memory bandwidth parameters Aditya Swarup
2021-01-28  5:30 ` Aditya Swarup [this message]
2021-01-29 17:27   ` [Intel-gfx] [PATCH 8/9] drm/i915/adl_s: Add display WAs for ADL-S Souza, Jose
2021-01-28  5:30 ` [Intel-gfx] [PATCH 9/9] drm/i915/adl_s: Add GT and CTX " Aditya Swarup
2021-01-28  5:53 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Final set of patches for ADLS enabling (rev2) Patchwork
2021-01-28  5:55 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-01-28  6:22 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-01-28  8:05 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-02-01 16:31   ` Souza, Jose
  -- strict thread matches above, loose matches on Subject: below --
2021-01-27  4:11 [Intel-gfx] [PATCH 0/9] Final set of patches for ADLS enabling Aditya Swarup
2021-01-27  4:11 ` [Intel-gfx] [PATCH 8/9] drm/i915/adl_s: Add display WAs for ADL-S Aditya Swarup
2021-01-27  5:22   ` Matt Roper
2021-01-28  5:43     ` Aditya Swarup
2021-01-29 17:26       ` Souza, Jose

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20210128053024.23540-9-aditya.swarup@intel.com \
    --to=aditya.swarup@intel.com \
    --cc=intel-gfx@lists.freedesktop.org \
    --cc=jani.nikula@intel.com \
    --cc=lucas.demarchi@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox