Intel-GFX Archive on lore.kernel.org
 help / color / mirror / Atom feed
From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Subject: [Intel-gfx] [PATCH v3 03/15] drm/i915: Extract hsw_ddi_{enable, disable}_clock()
Date: Fri,  5 Feb 2021 23:46:22 +0200	[thread overview]
Message-ID: <20210205214634.19341-4-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20210205214634.19341-1-ville.syrjala@linux.intel.com>

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Yank out the HSW/BDW code from intel_ddi_clk_{select,disable}()
and put it into the new encoder .{enable,disable}_clock() vfuncs.

v2: s/dev_priv/i915/ (Lucas)
v3: Deal with FDI

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> #v2
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_crt.c |  2 ++
 drivers/gpu/drm/i915/display/intel_ddi.c | 32 +++++++++++++++++++-----
 drivers/gpu/drm/i915/display/intel_ddi.h |  3 +++
 3 files changed, 31 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
index 077ebc7e6396..91a8a42b4aa2 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -1076,6 +1076,8 @@ void intel_crt_init(struct drm_i915_private *dev_priv)
 		crt->base.enable = hsw_enable_crt;
 		crt->base.disable = hsw_disable_crt;
 		crt->base.post_disable = hsw_post_disable_crt;
+		crt->base.enable_clock = hsw_ddi_enable_clock;
+		crt->base.disable_clock = hsw_ddi_disable_clock;
 	} else {
 		if (HAS_PCH_SPLIT(dev_priv)) {
 			crt->base.compute_config = pch_crt_compute_config;
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index ebfbd68b8e82..806712020530 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1896,9 +1896,6 @@ void intel_ddi_clk_select(struct intel_encoder *encoder,
 
 		intel_de_write(dev_priv, DPLL_CTRL2, val);
 
-	} else if (INTEL_GEN(dev_priv) < 9) {
-		intel_de_write(dev_priv, PORT_CLK_SEL(port),
-			       hsw_pll_to_ddi_pll_sel(pll));
 	}
 
 	mutex_unlock(&dev_priv->dpll.lock);
@@ -1921,12 +1918,30 @@ static void intel_ddi_clk_disable(struct intel_encoder *encoder)
 	} else if (IS_GEN9_BC(dev_priv)) {
 		intel_de_write(dev_priv, DPLL_CTRL2,
 			       intel_de_read(dev_priv, DPLL_CTRL2) | DPLL_CTRL2_DDI_CLK_OFF(port));
-	} else if (INTEL_GEN(dev_priv) < 9) {
-		intel_de_write(dev_priv, PORT_CLK_SEL(port),
-			       PORT_CLK_SEL_NONE);
 	}
 }
 
+void hsw_ddi_enable_clock(struct intel_encoder *encoder,
+			  const struct intel_crtc_state *crtc_state)
+{
+	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
+	enum port port = encoder->port;
+
+	if (drm_WARN_ON(&i915->drm, !pll))
+		return;
+
+	intel_de_write(i915, PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
+}
+
+void hsw_ddi_disable_clock(struct intel_encoder *encoder)
+{
+	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+	enum port port = encoder->port;
+
+	intel_de_write(i915, PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
+}
+
 void intel_ddi_enable_clock(struct intel_encoder *encoder,
 			    const struct intel_crtc_state *crtc_state)
 {
@@ -4073,6 +4088,11 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
 	encoder->cloneable = 0;
 	encoder->pipe_mask = ~0;
 
+	if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
+		encoder->enable_clock = hsw_ddi_enable_clock;
+		encoder->disable_clock = hsw_ddi_disable_clock;
+	}
+
 	if (IS_DG1(dev_priv))
 		encoder->hpd_pin = dg1_hpd_pin(dev_priv, port);
 	else if (IS_ROCKETLAKE(dev_priv))
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h b/drivers/gpu/drm/i915/display/intel_ddi.h
index 1aa0eedbf342..4a0c1d5c85e7 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.h
+++ b/drivers/gpu/drm/i915/display/intel_ddi.h
@@ -30,6 +30,9 @@ void intel_ddi_fdi_post_disable(struct intel_atomic_state *state,
 				const struct drm_connector_state *old_conn_state);
 void intel_ddi_enable_clock(struct intel_encoder *encoder,
 			    const struct intel_crtc_state *crtc_state);
+void hsw_ddi_enable_clock(struct intel_encoder *encoder,
+			  const struct intel_crtc_state *crtc_state);
+void hsw_ddi_disable_clock(struct intel_encoder *encoder);
 void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
 				  const struct intel_crtc_state *crtc_state);
 void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
-- 
2.26.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  parent reply	other threads:[~2021-02-05 21:46 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-02-05 21:46 [Intel-gfx] [PATCH v3 00/15] drm/i915: Clean up the DDI clock routing mess Ville Syrjala
2021-02-05 21:46 ` [Intel-gfx] [PATCH v3 01/15] drm/i915: Use intel_ddi_clk_select() for FDI Ville Syrjala
2021-02-13 17:33   ` Lucas De Marchi
2021-02-16 13:00     ` Ville Syrjälä
2021-02-05 21:46 ` [Intel-gfx] [PATCH v3 02/15] drm/i915: Introduce .{enable, disable}_clock() encoder vfuncs Ville Syrjala
2021-02-05 21:46 ` Ville Syrjala [this message]
2021-02-05 21:46 ` [Intel-gfx] [PATCH v3 04/15] drm/i915: Extract skl_ddi_{enable, disable}_clock() Ville Syrjala
2021-02-05 21:46 ` [Intel-gfx] [PATCH v3 05/15] drm/i195: Extract cnl_ddi_{enable, disable}_clock() Ville Syrjala
2021-02-05 21:46 ` [Intel-gfx] [PATCH v3 06/15] drm/i915: Convert DG1 over to .{enable, disable}_clock() Ville Syrjala
2021-02-05 21:46 ` [Intel-gfx] [PATCH v3 07/15] drm/i915: Extract icl+ .{enable, disable}_clock() vfuncs Ville Syrjala
2021-02-05 21:46 ` [Intel-gfx] [PATCH v3 08/15] drm/i915: Use intel_de_rmw() for DDI clock routing Ville Syrjala
2021-02-05 21:46 ` [Intel-gfx] [PATCH v3 09/15] drm/i915: Sprinkle a few missing locks around shared DDI clock registers Ville Syrjala
2021-02-05 21:46 ` [Intel-gfx] [PATCH v3 10/15] drm/i915: Sprinkle WARN(!pll) into icl/dg1 .clock_enable() Ville Syrjala
2021-02-05 21:46 ` [Intel-gfx] [PATCH v3 11/15] drm/i915: Extract _cnl_ddi_{enable, disable}_clock() Ville Syrjala
2021-02-05 21:46 ` [Intel-gfx] [PATCH v3 12/15] drm/i915: Split adl-s/rkl from icl_ddi_combo_{enable, disable}_clock() Ville Syrjala
2021-02-05 21:46 ` [Intel-gfx] [PATCH v3 13/15] drm/i915: Use .disable_clock() for pll sanitation Ville Syrjala
2021-02-05 21:46 ` [Intel-gfx] [PATCH v3 14/15] drm/i915: Relocate icl_sanitize_encoder_pll_mapping() Ville Syrjala
2021-02-05 21:46 ` [Intel-gfx] [PATCH v3 15/15] drm/i915: s/dev_priv/i915/ for the remainder of DDI clock routing Ville Syrjala
2021-02-13 17:34   ` Lucas De Marchi
2021-02-05 23:49 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Clean up the DDI clock routing mess (rev3) Patchwork
2021-02-05 23:50 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-02-06  0:20 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-02-06 11:51 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20210205214634.19341-4-ville.syrjala@linux.intel.com \
    --to=ville.syrjala@linux.intel.com \
    --cc=intel-gfx@lists.freedesktop.org \
    --cc=lucas.demarchi@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox