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From: Matt Roper <matthew.d.roper@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 25/56] drm/i915/adl_p: ADL_P device info enabling
Date: Thu, 11 Mar 2021 14:36:01 -0800	[thread overview]
Message-ID: <20210311223632.3191939-26-matthew.d.roper@intel.com> (raw)
In-Reply-To: <20210311223632.3191939-1-matthew.d.roper@intel.com>

From: Clinton Taylor <Clinton.A.Taylor@intel.com>

Add ADL-P to the device_info table and support MACROS.

Bspec: 49185, 55372, 55373
Cc: Matt Atwood <matthew.s.atwood@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 arch/x86/kernel/early-quirks.c           |  1 +
 drivers/gpu/drm/i915/i915_drv.h          |  1 +
 drivers/gpu/drm/i915/i915_pci.c          | 12 ++++++++++++
 drivers/gpu/drm/i915/intel_device_info.c |  1 +
 drivers/gpu/drm/i915/intel_device_info.h |  1 +
 5 files changed, 16 insertions(+)

diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
index 6edd1e2ee8af..b553ffe9b985 100644
--- a/arch/x86/kernel/early-quirks.c
+++ b/arch/x86/kernel/early-quirks.c
@@ -552,6 +552,7 @@ static const struct pci_device_id intel_early_ids[] __initconst = {
 	INTEL_TGL_12_IDS(&gen11_early_ops),
 	INTEL_RKL_IDS(&gen11_early_ops),
 	INTEL_ADLS_IDS(&gen11_early_ops),
+	INTEL_ADLP_IDS(&gen11_early_ops),
 };
 
 struct resource intel_graphics_stolen_res __ro_after_init = DEFINE_RES_MEM(0, 0);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 30103b22c086..b702e4f02ae7 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1383,6 +1383,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_ROCKETLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)
 #define IS_DG1(dev_priv)        IS_PLATFORM(dev_priv, INTEL_DG1)
 #define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_S)
+#define IS_ALDERLAKE_P(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_P)
 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
 				    (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
 #define IS_BDW_ULT(dev_priv) \
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 3f06502e1d85..dba6bedd258e 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -946,6 +946,17 @@ static const struct intel_device_info adl_s_info = {
 	.ddb_size = 4096,						\
 	.num_supported_dbuf_slices = 4
 
+static const struct intel_device_info adl_p_info = {
+	GEN12_FEATURES,
+	XE_LPD_FEATURES,
+	PLATFORM(INTEL_ALDERLAKE_P),
+	.require_force_probe = 1,
+	.platform_engine_mask =
+		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
+	.ppgtt_size = 48,
+	.dma_mask_size = 46,
+};
+
 #undef GEN
 #undef PLATFORM
 
@@ -1023,6 +1034,7 @@ static const struct pci_device_id pciidlist[] = {
 	INTEL_TGL_12_IDS(&tgl_info),
 	INTEL_RKL_IDS(&rkl_info),
 	INTEL_ADLS_IDS(&adl_s_info),
+	INTEL_ADLP_IDS(&adl_p_info),
 	{0, 0, 0}
 };
 MODULE_DEVICE_TABLE(pci, pciidlist);
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 8a55cdfc802c..16d8be7f734f 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -67,6 +67,7 @@ static const char * const platform_names[] = {
 	PLATFORM_NAME(ROCKETLAKE),
 	PLATFORM_NAME(DG1),
 	PLATFORM_NAME(ALDERLAKE_S),
+	PLATFORM_NAME(ALDERLAKE_P),
 };
 #undef PLATFORM_NAME
 
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 3c7db9c690f4..626cd11dab12 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -85,6 +85,7 @@ enum intel_platform {
 	INTEL_ROCKETLAKE,
 	INTEL_DG1,
 	INTEL_ALDERLAKE_S,
+	INTEL_ALDERLAKE_P,
 	INTEL_MAX_PLATFORMS
 };
 
-- 
2.25.4

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  parent reply	other threads:[~2021-03-11 22:37 UTC|newest]

Thread overview: 74+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-03-11 22:35 [Intel-gfx] [PATCH 00/56] Introduce Alder Lake-P Matt Roper
2021-03-11 22:35 ` [Intel-gfx] [PATCH 01/56] drm/i915/display: Convert gen5/gen6 tests to IS_IRONLAKE/IS_SANDYBRIDGE Matt Roper
2021-03-12 16:50   ` Ville Syrjälä
2021-03-11 22:35 ` [Intel-gfx] [PATCH 02/56] drm/i915: Add DISPLAY_VER() Matt Roper
2021-03-11 22:35 ` [Intel-gfx] [PATCH 03/56] drm/i915/display: Eliminate most usage of INTEL_GEN() Matt Roper
2021-03-11 22:35 ` [Intel-gfx] [PATCH 04/56] drm/i915: Convert INTEL_GEN() to DISPLAY_VER() as appropriate in intel_pm.c Matt Roper
2021-03-12 20:42   ` Srivatsa, Anusha
2021-03-12 20:46     ` Matt Roper
2021-03-17 18:02       ` Jani Nikula
2021-03-11 22:35 ` [Intel-gfx] [PATCH 05/56] drm/i915: Convert INTEL_GEN() to DISPLAY_VER() as appropriate in i915_irq.c Matt Roper
2021-03-11 22:35 ` [Intel-gfx] [PATCH 06/56] drm/i915/display: Simplify GLK display version tests Matt Roper
2021-03-12 18:52   ` Ville Syrjälä
2021-03-11 22:35 ` [Intel-gfx] [PATCH 07/56] drm/i915/xelpd: add XE_LPD display characteristics Matt Roper
2021-03-11 22:35 ` [Intel-gfx] [PATCH 08/56] drm/i915/xelpd: Handle proper AUX interrupt bits Matt Roper
2021-03-12 22:41   ` Srivatsa, Anusha
2021-03-11 22:35 ` [Intel-gfx] [PATCH 09/56] drm/i915/xelpd: Enhanced pipe underrun reporting Matt Roper
2021-03-11 22:35 ` [Intel-gfx] [PATCH 10/56] drm/i915/xelpd: Define plane capabilities Matt Roper
2021-03-11 22:35 ` [Intel-gfx] [PATCH 11/56] drm/i915/xelpd: Support 128k plane stride Matt Roper
2021-03-11 22:35 ` [Intel-gfx] [PATCH 12/56] drm/i915/xelpd: Handle new location of outputs D and E Matt Roper
2021-03-11 22:35 ` [Intel-gfx] [PATCH 13/56] drm/i915/xelpd: Add XE_LPD power wells Matt Roper
2021-03-11 22:35 ` [Intel-gfx] [PATCH 14/56] drm/i915/xelpd: Handle LPSP for XE_LPD Matt Roper
2021-03-11 22:35 ` [Intel-gfx] [PATCH 15/56] drm/i915/xelpd: Increase maximum watermark lines to 255 Matt Roper
2021-03-11 22:35 ` [Intel-gfx] [PATCH 16/56] drm/i915/xelpd: Required bandwidth increases when VT-d is active Matt Roper
2021-03-12 23:03   ` Srivatsa, Anusha
2021-03-11 22:35 ` [Intel-gfx] [PATCH 17/56] drm/i915/xelpd: Add Wa_14011503030 Matt Roper
2021-03-11 22:35 ` [Intel-gfx] [PATCH 18/56] drm/i915/display/dsc: Refactor intel_dp_dsc_compute_bpp Matt Roper
2021-03-11 22:35 ` [Intel-gfx] [PATCH 19/56] drm/i915/xelpd: Support DP1.4 compression BPPs Matt Roper
2021-03-11 22:35 ` [Intel-gfx] [PATCH 20/56] drm/i915: Get slice height before computing rc params Matt Roper
2021-03-11 22:35 ` [Intel-gfx] [PATCH 21/56] drm/i915/xelpd: Calculate VDSC RC parameters Matt Roper
2021-03-11 22:35 ` [Intel-gfx] [PATCH 22/56] drm/i915/xelpd: Add rc_qp_table for rcparams calculation Matt Roper
2021-03-11 22:35 ` [Intel-gfx] [PATCH 23/56] drm/i915/xelpd: Add VRR guardband for VRR CTL Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 24/56] drm/i915/adl_p: Add PCI Devices IDs Matt Roper
2021-03-12 23:20   ` Srivatsa, Anusha
2021-03-17 18:04   ` Jani Nikula
2021-03-11 22:36 ` Matt Roper [this message]
2021-03-11 22:36 ` [Intel-gfx] [PATCH 26/56] drm/i915/adl_p: Add PCH support Matt Roper
2021-03-12 23:52   ` Srivatsa, Anusha
2021-03-11 22:36 ` [Intel-gfx] [PATCH 27/56] drm/i915/adl_p: Add dedicated SAGV watermarks Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 28/56] drm/i915/adl_p: Extend PLANE_WM bits for blocks & lines Matt Roper
2021-03-12 23:59   ` Srivatsa, Anusha
2021-03-11 22:36 ` [Intel-gfx] [PATCH 29/56] drm/i915/adl_p: Load DMC Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 30/56] drm/i915/adl_p: Setup ports/phys Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 31/56] drm/i915/adl_p: Add cdclk support for ADL-P Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 32/56] drm/i915/display/tc: Rename safe_mode functions ownership Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 33/56] drm/i915/adl_p: Handle TC cold Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 34/56] drm/i915/adl_p: Implement TC sequences Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 35/56] drm/i915/adl_p: Enable modular fia Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 36/56] drm/i915/adl_p: Don't config MBUS and DBUF during display initialization Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 37/56] drm/i915/adl_p: Add ddb allocation support Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 38/56] drm/i915: Introduce MBUS relative dbuf offsets Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 39/56] drm/i915: Move intel_modeset_all_pipes() Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 40/56] drm/i915/adl_p: MBUS programming Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 41/56] drm/i915/adl_p: Tx escape clock with DSI Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 42/56] drm/i915/adl_p: Add initial ADL_P Workarounds Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 43/56] drm/i915/adlp: Define GuC/HuC for Alderlake_P Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 44/56] drm/i915/adl_p: Define and use ADL-P specific DP translation tables Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 45/56] drm/i915/adl_p: Enable/disable loadgen sharing Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 46/56] drm/i915/adl_p: Add PLL Support Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 47/56] drm/i915/bigjoiner: Mode validation with uncompressed pipe joiner Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 48/56] drm/i915/bigjoiner: Avoid dsc_compute_config for uncompressed bigjoiner Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 49/56] drm/i915/bigjoiner: atomic commit changes for uncompressed joiner Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 50/56] drm/i915/adlp: Add PIPE_MISC2 programming Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 51/56] drm/i915/adl_p: Update memory bandwidth parameters Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 52/56] drm/i915/adl_p: Implement Wa_22011091694 Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 53/56] drm/i915/display/adl_p: Implement Wa_22011320316 Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 54/56] drm/i915/display/adl_p: Remove CCS support Matt Roper
2021-03-13  0:24   ` Srivatsa, Anusha
2021-03-11 22:36 ` [Intel-gfx] [PATCH 55/56] drm/i915/perf: Enable OA formats for ADL_P Matt Roper
2021-03-12 20:37   ` Dixit, Ashutosh
2021-03-11 22:36 ` [Intel-gfx] [PATCH 56/56] drm/i915/display/adl_p: Implement PSR changes Matt Roper
2021-03-13 19:49   ` Mun, Gwan-gyeong
2021-03-11 22:48 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce Alder Lake-P Patchwork
2021-03-11 22:50 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-03-11 23:14 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork

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