From: Matt Roper <matthew.d.roper@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Subject: [Intel-gfx] [PATCH 08/56] drm/i915/xelpd: Handle proper AUX interrupt bits
Date: Thu, 11 Mar 2021 14:35:44 -0800 [thread overview]
Message-ID: <20210311223632.3191939-9-matthew.d.roper@intel.com> (raw)
In-Reply-To: <20210311223632.3191939-1-matthew.d.roper@intel.com>
XE_LPD has new AUX interrupt bits for DDI-D and DDI-E that take the
spots that were used by TC5/TC6 on Display12 platforms.
While we're at it, let's convert the bit definitions for all TGL+ aux
bits over to the modern REG_BIT() notation.
v2:
- Maintain bit order rather than logical order. (Lucas)
- Convert surrounding code to REG_BIT() notation. (Lucas)
Bspec: 50064
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 12 +++++++++++-
drivers/gpu/drm/i915/i915_reg.h | 20 +++++++++++---------
2 files changed, 22 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 23be88d59055..c9e03973502c 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2269,7 +2269,17 @@ static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv)
{
u32 mask;
- if (DISPLAY_VER(dev_priv) >= 12)
+ if (DISPLAY_VER(dev_priv) >= 13)
+ return TGL_DE_PORT_AUX_DDIA |
+ TGL_DE_PORT_AUX_DDIB |
+ TGL_DE_PORT_AUX_DDIC |
+ XELPD_DE_PORT_AUX_DDID |
+ XELPD_DE_PORT_AUX_DDIE |
+ TGL_DE_PORT_AUX_USBC1 |
+ TGL_DE_PORT_AUX_USBC2 |
+ TGL_DE_PORT_AUX_USBC3 |
+ TGL_DE_PORT_AUX_USBC4;
+ else if (DISPLAY_VER(dev_priv) >= 12)
return TGL_DE_PORT_AUX_DDIA |
TGL_DE_PORT_AUX_DDIB |
TGL_DE_PORT_AUX_DDIC |
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e5dd0203991b..475d14db2844 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7855,15 +7855,17 @@ enum {
#define BDW_DE_PORT_HOTPLUG_MASK GEN8_DE_PORT_HOTPLUG(HPD_PORT_A)
#define BXT_DE_PORT_GMBUS (1 << 1)
#define GEN8_AUX_CHANNEL_A (1 << 0)
-#define TGL_DE_PORT_AUX_USBC6 (1 << 13)
-#define TGL_DE_PORT_AUX_USBC5 (1 << 12)
-#define TGL_DE_PORT_AUX_USBC4 (1 << 11)
-#define TGL_DE_PORT_AUX_USBC3 (1 << 10)
-#define TGL_DE_PORT_AUX_USBC2 (1 << 9)
-#define TGL_DE_PORT_AUX_USBC1 (1 << 8)
-#define TGL_DE_PORT_AUX_DDIC (1 << 2)
-#define TGL_DE_PORT_AUX_DDIB (1 << 1)
-#define TGL_DE_PORT_AUX_DDIA (1 << 0)
+#define TGL_DE_PORT_AUX_USBC6 REG_BIT(13)
+#define XELPD_DE_PORT_AUX_DDIE REG_BIT(13)
+#define TGL_DE_PORT_AUX_USBC5 REG_BIT(12)
+#define XELPD_DE_PORT_AUX_DDID REG_BIT(12)
+#define TGL_DE_PORT_AUX_USBC4 REG_BIT(11)
+#define TGL_DE_PORT_AUX_USBC3 REG_BIT(10)
+#define TGL_DE_PORT_AUX_USBC2 REG_BIT(9)
+#define TGL_DE_PORT_AUX_USBC1 REG_BIT(8)
+#define TGL_DE_PORT_AUX_DDIC REG_BIT(2)
+#define TGL_DE_PORT_AUX_DDIB REG_BIT(1)
+#define TGL_DE_PORT_AUX_DDIA REG_BIT(0)
#define GEN8_DE_MISC_ISR _MMIO(0x44460)
#define GEN8_DE_MISC_IMR _MMIO(0x44464)
--
2.25.4
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next prev parent reply other threads:[~2021-03-11 22:37 UTC|newest]
Thread overview: 74+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-11 22:35 [Intel-gfx] [PATCH 00/56] Introduce Alder Lake-P Matt Roper
2021-03-11 22:35 ` [Intel-gfx] [PATCH 01/56] drm/i915/display: Convert gen5/gen6 tests to IS_IRONLAKE/IS_SANDYBRIDGE Matt Roper
2021-03-12 16:50 ` Ville Syrjälä
2021-03-11 22:35 ` [Intel-gfx] [PATCH 02/56] drm/i915: Add DISPLAY_VER() Matt Roper
2021-03-11 22:35 ` [Intel-gfx] [PATCH 03/56] drm/i915/display: Eliminate most usage of INTEL_GEN() Matt Roper
2021-03-11 22:35 ` [Intel-gfx] [PATCH 04/56] drm/i915: Convert INTEL_GEN() to DISPLAY_VER() as appropriate in intel_pm.c Matt Roper
2021-03-12 20:42 ` Srivatsa, Anusha
2021-03-12 20:46 ` Matt Roper
2021-03-17 18:02 ` Jani Nikula
2021-03-11 22:35 ` [Intel-gfx] [PATCH 05/56] drm/i915: Convert INTEL_GEN() to DISPLAY_VER() as appropriate in i915_irq.c Matt Roper
2021-03-11 22:35 ` [Intel-gfx] [PATCH 06/56] drm/i915/display: Simplify GLK display version tests Matt Roper
2021-03-12 18:52 ` Ville Syrjälä
2021-03-11 22:35 ` [Intel-gfx] [PATCH 07/56] drm/i915/xelpd: add XE_LPD display characteristics Matt Roper
2021-03-11 22:35 ` Matt Roper [this message]
2021-03-12 22:41 ` [Intel-gfx] [PATCH 08/56] drm/i915/xelpd: Handle proper AUX interrupt bits Srivatsa, Anusha
2021-03-11 22:35 ` [Intel-gfx] [PATCH 09/56] drm/i915/xelpd: Enhanced pipe underrun reporting Matt Roper
2021-03-11 22:35 ` [Intel-gfx] [PATCH 10/56] drm/i915/xelpd: Define plane capabilities Matt Roper
2021-03-11 22:35 ` [Intel-gfx] [PATCH 11/56] drm/i915/xelpd: Support 128k plane stride Matt Roper
2021-03-11 22:35 ` [Intel-gfx] [PATCH 12/56] drm/i915/xelpd: Handle new location of outputs D and E Matt Roper
2021-03-11 22:35 ` [Intel-gfx] [PATCH 13/56] drm/i915/xelpd: Add XE_LPD power wells Matt Roper
2021-03-11 22:35 ` [Intel-gfx] [PATCH 14/56] drm/i915/xelpd: Handle LPSP for XE_LPD Matt Roper
2021-03-11 22:35 ` [Intel-gfx] [PATCH 15/56] drm/i915/xelpd: Increase maximum watermark lines to 255 Matt Roper
2021-03-11 22:35 ` [Intel-gfx] [PATCH 16/56] drm/i915/xelpd: Required bandwidth increases when VT-d is active Matt Roper
2021-03-12 23:03 ` Srivatsa, Anusha
2021-03-11 22:35 ` [Intel-gfx] [PATCH 17/56] drm/i915/xelpd: Add Wa_14011503030 Matt Roper
2021-03-11 22:35 ` [Intel-gfx] [PATCH 18/56] drm/i915/display/dsc: Refactor intel_dp_dsc_compute_bpp Matt Roper
2021-03-11 22:35 ` [Intel-gfx] [PATCH 19/56] drm/i915/xelpd: Support DP1.4 compression BPPs Matt Roper
2021-03-11 22:35 ` [Intel-gfx] [PATCH 20/56] drm/i915: Get slice height before computing rc params Matt Roper
2021-03-11 22:35 ` [Intel-gfx] [PATCH 21/56] drm/i915/xelpd: Calculate VDSC RC parameters Matt Roper
2021-03-11 22:35 ` [Intel-gfx] [PATCH 22/56] drm/i915/xelpd: Add rc_qp_table for rcparams calculation Matt Roper
2021-03-11 22:35 ` [Intel-gfx] [PATCH 23/56] drm/i915/xelpd: Add VRR guardband for VRR CTL Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 24/56] drm/i915/adl_p: Add PCI Devices IDs Matt Roper
2021-03-12 23:20 ` Srivatsa, Anusha
2021-03-17 18:04 ` Jani Nikula
2021-03-11 22:36 ` [Intel-gfx] [PATCH 25/56] drm/i915/adl_p: ADL_P device info enabling Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 26/56] drm/i915/adl_p: Add PCH support Matt Roper
2021-03-12 23:52 ` Srivatsa, Anusha
2021-03-11 22:36 ` [Intel-gfx] [PATCH 27/56] drm/i915/adl_p: Add dedicated SAGV watermarks Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 28/56] drm/i915/adl_p: Extend PLANE_WM bits for blocks & lines Matt Roper
2021-03-12 23:59 ` Srivatsa, Anusha
2021-03-11 22:36 ` [Intel-gfx] [PATCH 29/56] drm/i915/adl_p: Load DMC Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 30/56] drm/i915/adl_p: Setup ports/phys Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 31/56] drm/i915/adl_p: Add cdclk support for ADL-P Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 32/56] drm/i915/display/tc: Rename safe_mode functions ownership Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 33/56] drm/i915/adl_p: Handle TC cold Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 34/56] drm/i915/adl_p: Implement TC sequences Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 35/56] drm/i915/adl_p: Enable modular fia Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 36/56] drm/i915/adl_p: Don't config MBUS and DBUF during display initialization Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 37/56] drm/i915/adl_p: Add ddb allocation support Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 38/56] drm/i915: Introduce MBUS relative dbuf offsets Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 39/56] drm/i915: Move intel_modeset_all_pipes() Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 40/56] drm/i915/adl_p: MBUS programming Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 41/56] drm/i915/adl_p: Tx escape clock with DSI Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 42/56] drm/i915/adl_p: Add initial ADL_P Workarounds Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 43/56] drm/i915/adlp: Define GuC/HuC for Alderlake_P Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 44/56] drm/i915/adl_p: Define and use ADL-P specific DP translation tables Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 45/56] drm/i915/adl_p: Enable/disable loadgen sharing Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 46/56] drm/i915/adl_p: Add PLL Support Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 47/56] drm/i915/bigjoiner: Mode validation with uncompressed pipe joiner Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 48/56] drm/i915/bigjoiner: Avoid dsc_compute_config for uncompressed bigjoiner Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 49/56] drm/i915/bigjoiner: atomic commit changes for uncompressed joiner Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 50/56] drm/i915/adlp: Add PIPE_MISC2 programming Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 51/56] drm/i915/adl_p: Update memory bandwidth parameters Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 52/56] drm/i915/adl_p: Implement Wa_22011091694 Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 53/56] drm/i915/display/adl_p: Implement Wa_22011320316 Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 54/56] drm/i915/display/adl_p: Remove CCS support Matt Roper
2021-03-13 0:24 ` Srivatsa, Anusha
2021-03-11 22:36 ` [Intel-gfx] [PATCH 55/56] drm/i915/perf: Enable OA formats for ADL_P Matt Roper
2021-03-12 20:37 ` Dixit, Ashutosh
2021-03-11 22:36 ` [Intel-gfx] [PATCH 56/56] drm/i915/display/adl_p: Implement PSR changes Matt Roper
2021-03-13 19:49 ` Mun, Gwan-gyeong
2021-03-11 22:48 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce Alder Lake-P Patchwork
2021-03-11 22:50 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-03-11 23:14 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
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