From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 08/17] drm/i915: Store the HDMI default entry in the bug trans struct
Date: Wed, 21 Apr 2021 19:48:40 +0300 [thread overview]
Message-ID: <20210421164849.12806-9-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20210421164849.12806-1-ville.syrjala@linux.intel.com>
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Store the default HDMI buf trans entry in struct intel_ddi_buf_trans
so that it's next to the actual table. This let's us start ridding
ourselves of some platofrm specifics in intel_ddi_hdmi_num_entries().
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
.../drm/i915/display/intel_ddi_buf_trans.c | 49 ++++++++++---------
.../drm/i915/display/intel_ddi_buf_trans.h | 1 +
2 files changed, 27 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
index d91b946dfa66..7574d6390a39 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
@@ -65,6 +65,7 @@ static const union intel_ddi_buf_trans_entry _hsw_ddi_translations_hdmi[] = {
static const struct intel_ddi_buf_trans hsw_ddi_translations_hdmi = {
.entries = _hsw_ddi_translations_hdmi,
.num_entries = ARRAY_SIZE(_hsw_ddi_translations_hdmi),
+ .hdmi_default_entry = 6,
};
static const union intel_ddi_buf_trans_entry _bdw_ddi_translations_edp[] = {
@@ -135,6 +136,7 @@ static const union intel_ddi_buf_trans_entry _bdw_ddi_translations_hdmi[] = {
static const struct intel_ddi_buf_trans bdw_ddi_translations_hdmi = {
.entries = _bdw_ddi_translations_hdmi,
.num_entries = ARRAY_SIZE(_bdw_ddi_translations_hdmi),
+ .hdmi_default_entry = 7,
};
/* Skylake H and S */
@@ -329,6 +331,7 @@ static const union intel_ddi_buf_trans_entry _skl_ddi_translations_hdmi[] = {
static const struct intel_ddi_buf_trans skl_ddi_translations_hdmi = {
.entries = _skl_ddi_translations_hdmi,
.num_entries = ARRAY_SIZE(_skl_ddi_translations_hdmi),
+ .hdmi_default_entry = 8,
};
/* Skylake/Kabylake Y */
@@ -349,6 +352,7 @@ static const union intel_ddi_buf_trans_entry _skl_y_ddi_translations_hdmi[] = {
static const struct intel_ddi_buf_trans skl_y_ddi_translations_hdmi = {
.entries = _skl_y_ddi_translations_hdmi,
.num_entries = ARRAY_SIZE(_skl_y_ddi_translations_hdmi),
+ .hdmi_default_entry = 8,
};
static const union intel_ddi_buf_trans_entry _bxt_ddi_translations_dp[] = {
@@ -409,6 +413,7 @@ static const union intel_ddi_buf_trans_entry _bxt_ddi_translations_hdmi[] = {
static const struct intel_ddi_buf_trans bxt_ddi_translations_hdmi = {
.entries = _bxt_ddi_translations_hdmi,
.num_entries = ARRAY_SIZE(_bxt_ddi_translations_hdmi),
+ .hdmi_default_entry = ARRAY_SIZE(_bxt_ddi_translations_hdmi) - 1,
};
/* Voltage Swing Programming for VccIO 0.85V for DP */
@@ -446,6 +451,7 @@ static const union intel_ddi_buf_trans_entry _cnl_ddi_translations_hdmi_0_85V[]
static const struct intel_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V = {
.entries = _cnl_ddi_translations_hdmi_0_85V,
.num_entries = ARRAY_SIZE(_cnl_ddi_translations_hdmi_0_85V),
+ .hdmi_default_entry = ARRAY_SIZE(_cnl_ddi_translations_hdmi_0_85V) - 1,
};
/* Voltage Swing Programming for VccIO 0.85V for eDP */
@@ -506,6 +512,7 @@ static const union intel_ddi_buf_trans_entry _cnl_ddi_translations_hdmi_0_95V[]
static const struct intel_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V = {
.entries = _cnl_ddi_translations_hdmi_0_95V,
.num_entries = ARRAY_SIZE(_cnl_ddi_translations_hdmi_0_95V),
+ .hdmi_default_entry = ARRAY_SIZE(_cnl_ddi_translations_hdmi_0_95V) - 1,
};
/* Voltage Swing Programming for VccIO 0.95V for eDP */
@@ -567,6 +574,7 @@ static const union intel_ddi_buf_trans_entry _cnl_ddi_translations_hdmi_1_05V[]
static const struct intel_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V = {
.entries = _cnl_ddi_translations_hdmi_1_05V,
.num_entries = ARRAY_SIZE(_cnl_ddi_translations_hdmi_1_05V),
+ .hdmi_default_entry = ARRAY_SIZE(_cnl_ddi_translations_hdmi_1_05V) - 1,
};
/* Voltage Swing Programming for VccIO 1.05V for eDP */
@@ -660,6 +668,7 @@ static const union intel_ddi_buf_trans_entry _icl_combo_phy_ddi_translations_hdm
static const struct intel_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi = {
.entries = _icl_combo_phy_ddi_translations_hdmi,
.num_entries = ARRAY_SIZE(_icl_combo_phy_ddi_translations_hdmi),
+ .hdmi_default_entry = ARRAY_SIZE(_icl_combo_phy_ddi_translations_hdmi) - 1,
};
static const union intel_ddi_buf_trans_entry _ehl_combo_phy_ddi_translations_dp[] = {
@@ -812,6 +821,7 @@ static const union intel_ddi_buf_trans_entry _icl_mg_phy_ddi_translations_hdmi[]
static const struct intel_ddi_buf_trans icl_mg_phy_ddi_translations_hdmi = {
.entries = _icl_mg_phy_ddi_translations_hdmi,
.num_entries = ARRAY_SIZE(_icl_mg_phy_ddi_translations_hdmi),
+ .hdmi_default_entry = ARRAY_SIZE(_icl_mg_phy_ddi_translations_hdmi) - 1,
};
static const union intel_ddi_buf_trans_entry _tgl_dkl_phy_ddi_translations_dp_hbr[] = {
@@ -869,6 +879,7 @@ static const union intel_ddi_buf_trans_entry _tgl_dkl_phy_ddi_translations_hdmi[
static const struct intel_ddi_buf_trans tgl_dkl_phy_ddi_translations_hdmi = {
.entries = _tgl_dkl_phy_ddi_translations_hdmi,
.num_entries = ARRAY_SIZE(_tgl_dkl_phy_ddi_translations_hdmi),
+ .hdmi_default_entry = ARRAY_SIZE(_tgl_dkl_phy_ddi_translations_hdmi) - 1,
};
static const union intel_ddi_buf_trans_entry _tgl_combo_phy_ddi_translations_dp_hbr[] = {
@@ -1629,42 +1640,34 @@ int intel_ddi_hdmi_num_entries(struct intel_encoder *encoder,
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
+ const struct intel_ddi_buf_trans *ddi_translations = NULL;
int n_entries;
if (DISPLAY_VER(dev_priv) >= 12) {
if (intel_phy_is_combo(dev_priv, phy))
- tgl_get_combo_buf_trans_hdmi(encoder, crtc_state, &n_entries);
+ ddi_translations = tgl_get_combo_buf_trans_hdmi(encoder, crtc_state, &n_entries);
else
- tgl_get_dkl_buf_trans_hdmi(encoder, crtc_state, &n_entries);
- *default_entry = n_entries - 1;
+ ddi_translations = tgl_get_dkl_buf_trans_hdmi(encoder, crtc_state, &n_entries);
} else if (DISPLAY_VER(dev_priv) == 11) {
if (intel_phy_is_combo(dev_priv, phy))
- icl_get_combo_buf_trans_hdmi(encoder, crtc_state, &n_entries);
+ ddi_translations = icl_get_combo_buf_trans_hdmi(encoder, crtc_state, &n_entries);
else
- icl_get_mg_buf_trans_hdmi(encoder, crtc_state, &n_entries);
- *default_entry = n_entries - 1;
+ ddi_translations = icl_get_mg_buf_trans_hdmi(encoder, crtc_state, &n_entries);
} else if (IS_CANNONLAKE(dev_priv)) {
- cnl_get_buf_trans_hdmi(encoder, &n_entries);
- *default_entry = n_entries - 1;
+ ddi_translations = cnl_get_buf_trans_hdmi(encoder, &n_entries);
} else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
- bxt_get_buf_trans_hdmi(encoder, &n_entries);
- *default_entry = n_entries - 1;
- } else if (DISPLAY_VER(dev_priv) == 9) {
- hsw_get_buf_trans_hdmi(encoder, &n_entries);
- *default_entry = 8;
- } else if (IS_BROADWELL(dev_priv)) {
- hsw_get_buf_trans_hdmi(encoder, &n_entries);
- *default_entry = 7;
- } else if (IS_HASWELL(dev_priv)) {
- hsw_get_buf_trans_hdmi(encoder, &n_entries);
- *default_entry = 6;
- } else {
- drm_WARN(&dev_priv->drm, 1, "ddi translation table missing\n");
- return 0;
+ ddi_translations = bxt_get_buf_trans_hdmi(encoder, &n_entries);
+ } else if (DISPLAY_VER(dev_priv) == 9 ||
+ IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
+ ddi_translations = hsw_get_buf_trans_hdmi(encoder, &n_entries);
}
- if (drm_WARN_ON_ONCE(&dev_priv->drm, n_entries == 0))
+ if (drm_WARN_ON(&dev_priv->drm, !ddi_translations)) {
+ *default_entry = 0;
return 0;
+ }
+
+ *default_entry = ddi_translations->hdmi_default_entry;
return n_entries;
}
diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
index 24072411e0b0..940140e64c76 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
+++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
@@ -56,6 +56,7 @@ union intel_ddi_buf_trans_entry {
struct intel_ddi_buf_trans {
const union intel_ddi_buf_trans_entry *entries;
u8 num_entries;
+ u8 hdmi_default_entry;
};
bool is_hobl_buf_trans(const struct intel_ddi_buf_trans *table);
--
2.26.3
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next prev parent reply other threads:[~2021-04-21 16:49 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-21 16:48 [Intel-gfx] [PATCH 00/17] drm/i915: DDI buf trans cleaup and fixes Ville Syrjala
2021-04-21 16:48 ` [Intel-gfx] [PATCH 01/17] drm/i915: s/intel/hsw/ for hsw/bde/skl buf trans Ville Syrjala
2021-04-21 16:48 ` [Intel-gfx] [PATCH 02/17] drm/i915: Introduce hsw_get_buf_trans() Ville Syrjala
2021-04-21 16:48 ` [Intel-gfx] [PATCH 03/17] drm/i915: Wrap the platform specific buf trans structs into a union Ville Syrjala
2021-04-21 16:48 ` [Intel-gfx] [PATCH 04/17] drm/i915: Rename dkl phy buf trans tables Ville Syrjala
2021-04-21 16:48 ` [Intel-gfx] [PATCH 05/17] drm/i915: Wrap the buf trans tables into a struct Ville Syrjala
2021-04-21 16:48 ` [Intel-gfx] [PATCH 06/17] drm/i915: Introduce intel_get_buf_trans() Ville Syrjala
2021-04-21 16:48 ` [Intel-gfx] [PATCH 07/17] drm/i915; Return the whole buf_trans struct from get_buf_trans() Ville Syrjala
2021-04-21 16:48 ` Ville Syrjala [this message]
2021-04-21 16:48 ` [Intel-gfx] [PATCH 09/17] drm/i915: Introduce encoder->get_buf_trans() Ville Syrjala
2021-05-11 18:31 ` Jani Nikula
2021-04-21 16:48 ` [Intel-gfx] [PATCH 10/17] drm/i915: Clean up hsw/bdw/skl/kbl buf trans funcs Ville Syrjala
2021-05-12 18:53 ` Jani Nikula
2021-04-21 16:48 ` [Intel-gfx] [PATCH 11/17] drm/i915: Introduce rkl_get_combo_buf_trans() Ville Syrjala
2021-05-12 18:58 ` Jani Nikula
2021-04-21 16:48 ` [Intel-gfx] [PATCH 12/17] drm/i915: Fix dg1 buf trans tables Ville Syrjala
2021-05-04 10:15 ` [Intel-gfx] [PATCH v2 " Ville Syrjala
2021-05-12 19:05 ` Jani Nikula
2021-04-21 16:48 ` [Intel-gfx] [PATCH 13/17] drm/i915: Deduplicate icl DP HBR2 vs. eDP HBR3 table Ville Syrjala
2021-04-21 16:48 ` [Intel-gfx] [PATCH 14/17] drm/i915: Fix ehl edp hbr2 vswing table Ville Syrjala
2021-04-21 16:48 ` [Intel-gfx] [PATCH 15/17] drm/i915: Clean up jsl/ehl buf trans functions Ville Syrjala
2021-04-21 16:48 ` [Intel-gfx] [PATCH 16/17] drm/i915: Nuke buf_trans hdmi functions Ville Syrjala
2021-04-21 16:48 ` [Intel-gfx] [PATCH 17/17] drm/i915: Add the missing adls vswing tables Ville Syrjala
2021-04-22 6:20 ` kernel test robot
2021-05-04 10:16 ` [Intel-gfx] [PATCH v2 " Ville Syrjala
2021-04-21 17:17 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: DDI buf trans cleaup and fixes Patchwork
2021-04-21 17:18 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-04-21 17:22 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
2021-04-21 17:45 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-04-22 1:15 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-05-04 12:13 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: DDI buf trans cleaup and fixes (rev3) Patchwork
2021-05-04 12:14 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-05-04 12:41 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-05-04 14:05 ` [Intel-gfx] [PATCH 00/17] drm/i915: DDI buf trans cleaup and fixes Jani Nikula
2021-05-04 14:18 ` [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: DDI buf trans cleaup and fixes (rev3) Patchwork
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