From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v2 17/17] drm/i915: Add the missing adls vswing tables
Date: Tue, 4 May 2021 13:16:22 +0300 [thread overview]
Message-ID: <20210504101622.26212-1-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20210421164849.12806-18-ville.syrjala@linux.intel.com>
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
adls is supposed to use special buf trans tables. Add what's
missing.
v2: Drop the RBR/HBR table since it's the same as for tgl
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
.../drm/i915/display/intel_ddi_buf_trans.c | 103 +++++++++++++++++-
1 file changed, 102 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
index d38bf04cf23c..189a93b8277e 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
@@ -999,6 +999,63 @@ static const struct intel_ddi_buf_trans rkl_combo_phy_ddi_translations_dp_hbr2_h
.num_entries = ARRAY_SIZE(_rkl_combo_phy_ddi_translations_dp_hbr2_hbr3),
};
+static const union intel_ddi_buf_trans_entry _adls_combo_phy_ddi_translations_dp_hbr2_hbr3[] = {
+ /* NT mV Trans mV db */
+ { .cnl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */
+ { .cnl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350 500 3.1 */
+ { .cnl = { 0xC, 0x63, 0x30, 0x00, 0x0F } }, /* 350 700 6.0 */
+ { .cnl = { 0x6, 0x7F, 0x2B, 0x00, 0x14 } }, /* 350 900 8.2 */
+ { .cnl = { 0xA, 0x47, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */
+ { .cnl = { 0xC, 0x63, 0x37, 0x00, 0x08 } }, /* 500 700 2.9 */
+ { .cnl = { 0x6, 0x7F, 0x31, 0x00, 0x0E } }, /* 500 900 5.1 */
+ { .cnl = { 0xC, 0x61, 0x3C, 0x00, 0x03 } }, /* 650 700 0.6 */
+ { .cnl = { 0x6, 0x7B, 0x35, 0x00, 0x0A } }, /* 600 900 3.5 */
+ { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */
+};
+
+static const struct intel_ddi_buf_trans adls_combo_phy_ddi_translations_dp_hbr2_hbr3 = {
+ .entries = _adls_combo_phy_ddi_translations_dp_hbr2_hbr3,
+ .num_entries = ARRAY_SIZE(_adls_combo_phy_ddi_translations_dp_hbr2_hbr3),
+};
+
+static const union intel_ddi_buf_trans_entry _adls_combo_phy_ddi_translations_edp_hbr2[] = {
+ /* NT mV Trans mV db */
+ { .cnl = { 0x9, 0x70, 0x3C, 0x00, 0x03 } }, /* 200 200 0.0 */
+ { .cnl = { 0x9, 0x6D, 0x3A, 0x00, 0x05 } }, /* 200 250 1.9 */
+ { .cnl = { 0x9, 0x7F, 0x36, 0x00, 0x09 } }, /* 200 300 3.5 */
+ { .cnl = { 0x4, 0x59, 0x32, 0x00, 0x0D } }, /* 200 350 4.9 */
+ { .cnl = { 0x2, 0x77, 0x3A, 0x00, 0x05 } }, /* 250 250 0.0 */
+ { .cnl = { 0x2, 0x7F, 0x38, 0x00, 0x07 } }, /* 250 300 1.6 */
+ { .cnl = { 0x4, 0x5A, 0x36, 0x00, 0x09 } }, /* 250 350 2.9 */
+ { .cnl = { 0x4, 0x5E, 0x3D, 0x00, 0x04 } }, /* 300 300 0.0 */
+ { .cnl = { 0x4, 0x65, 0x38, 0x00, 0x07 } }, /* 300 350 1.3 */
+ { .cnl = { 0x4, 0x6F, 0x3A, 0x00, 0x05 } }, /* 350 350 0.0 */
+};
+
+static const struct intel_ddi_buf_trans adls_combo_phy_ddi_translations_edp_hbr2 = {
+ .entries = _adls_combo_phy_ddi_translations_edp_hbr2,
+ .num_entries = ARRAY_SIZE(_adls_combo_phy_ddi_translations_edp_hbr2),
+};
+
+static const union intel_ddi_buf_trans_entry _adls_combo_phy_ddi_translations_edp_hbr3[] = {
+ /* NT mV Trans mV db */
+ { .cnl = { 0xA, 0x5E, 0x34, 0x00, 0x0B } }, /* 350 350 0.0 */
+ { .cnl = { 0xA, 0x69, 0x32, 0x00, 0x0D } }, /* 350 500 3.1 */
+ { .cnl = { 0xC, 0x74, 0x31, 0x00, 0x0E } }, /* 350 700 6.0 */
+ { .cnl = { 0x6, 0x7F, 0x2E, 0x00, 0x11 } }, /* 350 900 8.2 */
+ { .cnl = { 0xA, 0x5C, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */
+ { .cnl = { 0xC, 0x7F, 0x34, 0x00, 0x0B } }, /* 500 700 2.9 */
+ { .cnl = { 0x6, 0x7F, 0x33, 0x00, 0x0C } }, /* 500 900 5.1 */
+ { .cnl = { 0xC, 0x7F, 0x3F, 0x00, 0x00 } }, /* 650 700 0.6 */
+ { .cnl = { 0x6, 0x7F, 0x3C, 0x00, 0x03 } }, /* 600 900 3.5 */
+ { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */
+};
+
+static const struct intel_ddi_buf_trans adls_combo_phy_ddi_translations_edp_hbr3 = {
+ .entries = _adls_combo_phy_ddi_translations_edp_hbr3,
+ .num_entries = ARRAY_SIZE(_adls_combo_phy_ddi_translations_edp_hbr3),
+};
+
bool is_hobl_buf_trans(const struct intel_ddi_buf_trans *table)
{
return table == &tgl_combo_phy_ddi_translations_edp_hbr2_hobl;
@@ -1524,6 +1581,48 @@ rkl_get_combo_buf_trans(struct intel_encoder *encoder,
return rkl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
}
+static const struct intel_ddi_buf_trans *
+adls_get_combo_buf_trans_dp(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
+ int *n_entries)
+{
+ if (crtc_state->port_clock > 270000)
+ return intel_get_buf_trans(&adls_combo_phy_ddi_translations_dp_hbr2_hbr3, n_entries);
+ else
+ return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_dp_hbr, n_entries);
+}
+
+static const struct intel_ddi_buf_trans *
+adls_get_combo_buf_trans_edp(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
+ int *n_entries)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+
+ if (crtc_state->port_clock > 540000)
+ return intel_get_buf_trans(&adls_combo_phy_ddi_translations_edp_hbr3, n_entries);
+ else if (i915->vbt.edp.hobl && !intel_dp->hobl_failed)
+ return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_edp_hbr2_hobl, n_entries);
+ else if (i915->vbt.edp.low_vswing)
+ return intel_get_buf_trans(&adls_combo_phy_ddi_translations_edp_hbr2, n_entries);
+ else
+ return adls_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
+}
+
+static const struct intel_ddi_buf_trans *
+adls_get_combo_buf_trans(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
+ int *n_entries)
+{
+ if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
+ return intel_get_buf_trans(&icl_combo_phy_ddi_translations_hdmi, n_entries);
+ else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
+ return adls_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
+ else
+ return adls_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
+}
+
static const struct intel_ddi_buf_trans *
tgl_get_dkl_buf_trans_dp(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
@@ -1574,7 +1673,9 @@ void intel_ddi_buf_trans_init(struct intel_encoder *encoder)
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
enum phy phy = intel_port_to_phy(i915, encoder->port);
- if (IS_ROCKETLAKE(i915)) {
+ if (IS_ALDERLAKE_S(i915)) {
+ encoder->get_buf_trans = adls_get_combo_buf_trans;
+ } else if (IS_ROCKETLAKE(i915)) {
encoder->get_buf_trans = rkl_get_combo_buf_trans;
} else if (IS_DG1(i915)) {
encoder->get_buf_trans = dg1_get_combo_buf_trans;
--
2.26.3
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next prev parent reply other threads:[~2021-05-04 10:16 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-21 16:48 [Intel-gfx] [PATCH 00/17] drm/i915: DDI buf trans cleaup and fixes Ville Syrjala
2021-04-21 16:48 ` [Intel-gfx] [PATCH 01/17] drm/i915: s/intel/hsw/ for hsw/bde/skl buf trans Ville Syrjala
2021-04-21 16:48 ` [Intel-gfx] [PATCH 02/17] drm/i915: Introduce hsw_get_buf_trans() Ville Syrjala
2021-04-21 16:48 ` [Intel-gfx] [PATCH 03/17] drm/i915: Wrap the platform specific buf trans structs into a union Ville Syrjala
2021-04-21 16:48 ` [Intel-gfx] [PATCH 04/17] drm/i915: Rename dkl phy buf trans tables Ville Syrjala
2021-04-21 16:48 ` [Intel-gfx] [PATCH 05/17] drm/i915: Wrap the buf trans tables into a struct Ville Syrjala
2021-04-21 16:48 ` [Intel-gfx] [PATCH 06/17] drm/i915: Introduce intel_get_buf_trans() Ville Syrjala
2021-04-21 16:48 ` [Intel-gfx] [PATCH 07/17] drm/i915; Return the whole buf_trans struct from get_buf_trans() Ville Syrjala
2021-04-21 16:48 ` [Intel-gfx] [PATCH 08/17] drm/i915: Store the HDMI default entry in the bug trans struct Ville Syrjala
2021-04-21 16:48 ` [Intel-gfx] [PATCH 09/17] drm/i915: Introduce encoder->get_buf_trans() Ville Syrjala
2021-05-11 18:31 ` Jani Nikula
2021-04-21 16:48 ` [Intel-gfx] [PATCH 10/17] drm/i915: Clean up hsw/bdw/skl/kbl buf trans funcs Ville Syrjala
2021-05-12 18:53 ` Jani Nikula
2021-04-21 16:48 ` [Intel-gfx] [PATCH 11/17] drm/i915: Introduce rkl_get_combo_buf_trans() Ville Syrjala
2021-05-12 18:58 ` Jani Nikula
2021-04-21 16:48 ` [Intel-gfx] [PATCH 12/17] drm/i915: Fix dg1 buf trans tables Ville Syrjala
2021-05-04 10:15 ` [Intel-gfx] [PATCH v2 " Ville Syrjala
2021-05-12 19:05 ` Jani Nikula
2021-04-21 16:48 ` [Intel-gfx] [PATCH 13/17] drm/i915: Deduplicate icl DP HBR2 vs. eDP HBR3 table Ville Syrjala
2021-04-21 16:48 ` [Intel-gfx] [PATCH 14/17] drm/i915: Fix ehl edp hbr2 vswing table Ville Syrjala
2021-04-21 16:48 ` [Intel-gfx] [PATCH 15/17] drm/i915: Clean up jsl/ehl buf trans functions Ville Syrjala
2021-04-21 16:48 ` [Intel-gfx] [PATCH 16/17] drm/i915: Nuke buf_trans hdmi functions Ville Syrjala
2021-04-21 16:48 ` [Intel-gfx] [PATCH 17/17] drm/i915: Add the missing adls vswing tables Ville Syrjala
2021-04-22 6:20 ` kernel test robot
2021-05-04 10:16 ` Ville Syrjala [this message]
2021-04-21 17:17 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: DDI buf trans cleaup and fixes Patchwork
2021-04-21 17:18 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-04-21 17:22 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
2021-04-21 17:45 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-04-22 1:15 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-05-04 12:13 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: DDI buf trans cleaup and fixes (rev3) Patchwork
2021-05-04 12:14 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-05-04 12:41 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-05-04 14:05 ` [Intel-gfx] [PATCH 00/17] drm/i915: DDI buf trans cleaup and fixes Jani Nikula
2021-05-04 14:18 ` [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: DDI buf trans cleaup and fixes (rev3) Patchwork
-- strict thread matches above, loose matches on Subject: below --
2021-06-08 7:35 [Intel-gfx] [PATCH v2 00/17] drm/i915: DDI buf trans cleaup and fixes Ville Syrjala
2021-06-08 7:36 ` [Intel-gfx] [PATCH v2 17/17] drm/i915: Add the missing adls vswing tables Ville Syrjala
2021-06-23 14:36 ` Jani Nikula
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