public inbox for intel-gfx@lists.freedesktop.org
 help / color / mirror / Atom feed
From: Jani Nikula <jani.nikula@linux.intel.com>
To: Ville Syrjala <ville.syrjala@linux.intel.com>,
	intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 11/17] drm/i915: Introduce rkl_get_combo_buf_trans()
Date: Wed, 12 May 2021 21:58:51 +0300	[thread overview]
Message-ID: <87fsyru6c4.fsf@intel.com> (raw)
In-Reply-To: <20210421164849.12806-12-ville.syrjala@linux.intel.com>

On Wed, 21 Apr 2021, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Give RKL its own get_buf_trans() func.
>
> Note that the spec currently only lists values for DP.
> Until we get that clarified let's just assume that for
> HDMI and eDP we should do what TGL does (except we fall
> back to the RKL DP values instead of TGL DP values when
> not using the eDP specific values, whereas previously
> we used all TGL values for eDP).
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> ---
>  .../drm/i915/display/intel_ddi_buf_trans.c    | 65 +++++++++++++++----
>  1 file changed, 53 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> index 1d78640c439e..fd55c812f14a 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> @@ -1458,10 +1458,7 @@ tgl_get_combo_buf_trans_dp(struct intel_encoder *encoder,
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  
>  	if (crtc_state->port_clock > 270000) {
> -		if (IS_ROCKETLAKE(dev_priv)) {
> -			return intel_get_buf_trans(&rkl_combo_phy_ddi_translations_dp_hbr2_hbr3,
> -						   n_entries);
> -		} else if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) {
> +		if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) {
>  			return intel_get_buf_trans(&tgl_uy_combo_phy_ddi_translations_dp_hbr2,
>  						   n_entries);
>  		} else {
> @@ -1469,13 +1466,8 @@ tgl_get_combo_buf_trans_dp(struct intel_encoder *encoder,
>  						   n_entries);
>  		}
>  	} else {
> -		if (IS_ROCKETLAKE(dev_priv)) {
> -			return intel_get_buf_trans(&rkl_combo_phy_ddi_translations_dp_hbr,
> -						   n_entries);
> -		} else {
> -			return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_dp_hbr,
> -						   n_entries);
> -		}
> +		return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_dp_hbr,
> +					   n_entries);
>  	}
>  }
>  
> @@ -1514,6 +1506,53 @@ tgl_get_combo_buf_trans(struct intel_encoder *encoder,
>  		return tgl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
>  }
>  
> +static const struct intel_ddi_buf_trans *
> +rkl_get_combo_buf_trans_dp(struct intel_encoder *encoder,
> +			   const struct intel_crtc_state *crtc_state,
> +			   int *n_entries)
> +{
> +	if (crtc_state->port_clock > 270000)
> +		return intel_get_buf_trans(&rkl_combo_phy_ddi_translations_dp_hbr2_hbr3, n_entries);
> +	else
> +		return intel_get_buf_trans(&rkl_combo_phy_ddi_translations_dp_hbr, n_entries);
> +}
> +
> +static const struct intel_ddi_buf_trans *
> +rkl_get_combo_buf_trans_edp(struct intel_encoder *encoder,
> +			    const struct intel_crtc_state *crtc_state,
> +			    int *n_entries)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> +
> +	if (crtc_state->port_clock > 540000) {
> +		return intel_get_buf_trans(&icl_combo_phy_ddi_translations_edp_hbr3,
> +					   n_entries);
> +	} else if (dev_priv->vbt.edp.hobl && !intel_dp->hobl_failed) {
> +		return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_edp_hbr2_hobl,
> +					   n_entries);
> +	} else if (dev_priv->vbt.edp.low_vswing) {
> +		return intel_get_buf_trans(&icl_combo_phy_ddi_translations_edp_hbr2,
> +					   n_entries);
> +	}
> +
> +	return rkl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
> +}
> +
> +static const struct intel_ddi_buf_trans *
> +rkl_get_combo_buf_trans(struct intel_encoder *encoder,
> +			const struct intel_crtc_state *crtc_state,
> +			int *n_entries)
> +{
> +	/* FIXME unclear what values we should use for HDMI and eDP */
> +	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
> +		return tgl_get_combo_buf_trans_hdmi(encoder, crtc_state, n_entries);
> +	else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
> +		return rkl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
> +	else
> +		return rkl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
> +}
> +
>  static const struct intel_ddi_buf_trans *
>  tgl_get_dkl_buf_trans_hdmi(struct intel_encoder *encoder,
>  			   const struct intel_crtc_state *crtc_state,
> @@ -1573,7 +1612,9 @@ void intel_ddi_buf_trans_init(struct intel_encoder *encoder)
>  	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
>  	enum phy phy = intel_port_to_phy(i915, encoder->port);
>  
> -	if (DISPLAY_VER(i915) >= 12) {
> +	if (IS_ROCKETLAKE(i915)) {
> +		encoder->get_buf_trans = rkl_get_combo_buf_trans;
> +	} else if (DISPLAY_VER(i915) >= 12) {
>  		if (intel_phy_is_combo(i915, phy))
>  			encoder->get_buf_trans = tgl_get_combo_buf_trans;
>  		else

-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2021-05-12 18:59 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-21 16:48 [Intel-gfx] [PATCH 00/17] drm/i915: DDI buf trans cleaup and fixes Ville Syrjala
2021-04-21 16:48 ` [Intel-gfx] [PATCH 01/17] drm/i915: s/intel/hsw/ for hsw/bde/skl buf trans Ville Syrjala
2021-04-21 16:48 ` [Intel-gfx] [PATCH 02/17] drm/i915: Introduce hsw_get_buf_trans() Ville Syrjala
2021-04-21 16:48 ` [Intel-gfx] [PATCH 03/17] drm/i915: Wrap the platform specific buf trans structs into a union Ville Syrjala
2021-04-21 16:48 ` [Intel-gfx] [PATCH 04/17] drm/i915: Rename dkl phy buf trans tables Ville Syrjala
2021-04-21 16:48 ` [Intel-gfx] [PATCH 05/17] drm/i915: Wrap the buf trans tables into a struct Ville Syrjala
2021-04-21 16:48 ` [Intel-gfx] [PATCH 06/17] drm/i915: Introduce intel_get_buf_trans() Ville Syrjala
2021-04-21 16:48 ` [Intel-gfx] [PATCH 07/17] drm/i915; Return the whole buf_trans struct from get_buf_trans() Ville Syrjala
2021-04-21 16:48 ` [Intel-gfx] [PATCH 08/17] drm/i915: Store the HDMI default entry in the bug trans struct Ville Syrjala
2021-04-21 16:48 ` [Intel-gfx] [PATCH 09/17] drm/i915: Introduce encoder->get_buf_trans() Ville Syrjala
2021-05-11 18:31   ` Jani Nikula
2021-04-21 16:48 ` [Intel-gfx] [PATCH 10/17] drm/i915: Clean up hsw/bdw/skl/kbl buf trans funcs Ville Syrjala
2021-05-12 18:53   ` Jani Nikula
2021-04-21 16:48 ` [Intel-gfx] [PATCH 11/17] drm/i915: Introduce rkl_get_combo_buf_trans() Ville Syrjala
2021-05-12 18:58   ` Jani Nikula [this message]
2021-04-21 16:48 ` [Intel-gfx] [PATCH 12/17] drm/i915: Fix dg1 buf trans tables Ville Syrjala
2021-05-04 10:15   ` [Intel-gfx] [PATCH v2 " Ville Syrjala
2021-05-12 19:05     ` Jani Nikula
2021-04-21 16:48 ` [Intel-gfx] [PATCH 13/17] drm/i915: Deduplicate icl DP HBR2 vs. eDP HBR3 table Ville Syrjala
2021-04-21 16:48 ` [Intel-gfx] [PATCH 14/17] drm/i915: Fix ehl edp hbr2 vswing table Ville Syrjala
2021-04-21 16:48 ` [Intel-gfx] [PATCH 15/17] drm/i915: Clean up jsl/ehl buf trans functions Ville Syrjala
2021-04-21 16:48 ` [Intel-gfx] [PATCH 16/17] drm/i915: Nuke buf_trans hdmi functions Ville Syrjala
2021-04-21 16:48 ` [Intel-gfx] [PATCH 17/17] drm/i915: Add the missing adls vswing tables Ville Syrjala
2021-04-22  6:20   ` kernel test robot
2021-05-04 10:16   ` [Intel-gfx] [PATCH v2 " Ville Syrjala
2021-04-21 17:17 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: DDI buf trans cleaup and fixes Patchwork
2021-04-21 17:18 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-04-21 17:22 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
2021-04-21 17:45 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-04-22  1:15 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-05-04 12:13 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: DDI buf trans cleaup and fixes (rev3) Patchwork
2021-05-04 12:14 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-05-04 12:41 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-05-04 14:05 ` [Intel-gfx] [PATCH 00/17] drm/i915: DDI buf trans cleaup and fixes Jani Nikula
2021-05-04 14:18 ` [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: DDI buf trans cleaup and fixes (rev3) Patchwork

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=87fsyru6c4.fsf@intel.com \
    --to=jani.nikula@linux.intel.com \
    --cc=intel-gfx@lists.freedesktop.org \
    --cc=ville.syrjala@linux.intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox