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From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 2/5] drm/i915: Use intel_de_rmw() in bdw cdclk programming
Date: Fri, 30 Apr 2021 18:34:41 +0300	[thread overview]
Message-ID: <20210430153444.29270-3-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20210430153444.29270-1-ville.syrjala@linux.intel.com>

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Replace the hand rolled rmw sequences with intel_de_rmw().

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 17 ++++++-----------
 1 file changed, 6 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index d5314f9acf83..1ef8da2bf856 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -745,7 +745,6 @@ static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
 			  enum pipe pipe)
 {
 	int cdclk = cdclk_config->cdclk;
-	u32 val;
 	int ret;
 
 	if (drm_WARN(&dev_priv->drm,
@@ -765,9 +764,8 @@ static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
 		return;
 	}
 
-	val = intel_de_read(dev_priv, LCPLL_CTL);
-	val |= LCPLL_CD_SOURCE_FCLK;
-	intel_de_write(dev_priv, LCPLL_CTL, val);
+	intel_de_rmw(dev_priv, LCPLL_CTL,
+		     0, LCPLL_CD_SOURCE_FCLK);
 
 	/*
 	 * According to the spec, it should be enough to poll for this 1 us.
@@ -777,14 +775,11 @@ static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
 			LCPLL_CD_SOURCE_FCLK_DONE, 100))
 		drm_err(&dev_priv->drm, "Switching to FCLK failed\n");
 
-	val = intel_de_read(dev_priv, LCPLL_CTL);
-	val &= ~LCPLL_CLK_FREQ_MASK;
-	val |= bdw_cdclk_freq_sel(cdclk);
-	intel_de_write(dev_priv, LCPLL_CTL, val);
+	intel_de_rmw(dev_priv, LCPLL_CTL,
+		     LCPLL_CLK_FREQ_MASK, bdw_cdclk_freq_sel(cdclk));
 
-	val = intel_de_read(dev_priv, LCPLL_CTL);
-	val &= ~LCPLL_CD_SOURCE_FCLK;
-	intel_de_write(dev_priv, LCPLL_CTL, val);
+	intel_de_rmw(dev_priv, LCPLL_CTL,
+		     LCPLL_CD_SOURCE_FCLK, 0);
 
 	if (wait_for_us((intel_de_read(dev_priv, LCPLL_CTL) &
 			 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
-- 
2.26.3

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  parent reply	other threads:[~2021-04-30 15:34 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-30 15:34 [Intel-gfx] [PATCH 0/5] drm/i915: cdclk cleanups Ville Syrjala
2021-04-30 15:34 ` [Intel-gfx] [PATCH 1/5] drm/i915: Extract some helpers to compute cdclk register values Ville Syrjala
2021-04-30 15:34 ` Ville Syrjala [this message]
2021-05-03 17:53   ` [Intel-gfx] [PATCH 2/5] drm/i915: Use intel_de_rmw() in bdw cdclk programming Jani Nikula
2021-04-30 15:34 ` [Intel-gfx] [PATCH 3/5] drm/i915: Use intel_de_rmw() in skl " Ville Syrjala
2021-04-30 15:34 ` [Intel-gfx] [PATCH 4/5] drm/i915: Use intel_de_rmw() in bxt/glk/cnl+ " Ville Syrjala
2021-04-30 15:34 ` [Intel-gfx] [PATCH 5/5] drm/i915: Use intel_de_wait_for_*() in cnl+ " Ville Syrjala
2021-05-03 12:46 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: cdclk cleanups Patchwork
2021-05-03 14:47 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-05-03 17:55 ` [Intel-gfx] [PATCH 0/5] " Jani Nikula

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