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From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 3/5] drm/i915: Use intel_de_rmw() in skl cdclk programming
Date: Fri, 30 Apr 2021 18:34:42 +0300	[thread overview]
Message-ID: <20210430153444.29270-4-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20210430153444.29270-1-ville.syrjala@linux.intel.com>

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Replace the hand rolled rmw sequences with intel_de_rmw().

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 25 ++++++++++------------
 1 file changed, 11 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 1ef8da2bf856..d7d051968af6 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -969,20 +969,16 @@ static u32 skl_dpll0_link_rate(struct drm_i915_private *dev_priv, int vco)
 
 static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
 {
-	u32 val;
-
-	val = intel_de_read(dev_priv, DPLL_CTRL1);
-
-	val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
-		 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
-	val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
-	val |= skl_dpll0_link_rate(dev_priv, vco);
-
-	intel_de_write(dev_priv, DPLL_CTRL1, val);
+	intel_de_rmw(dev_priv, DPLL_CTRL1,
+		     DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
+		     DPLL_CTRL1_SSC(SKL_DPLL0) |
+		     DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0),
+		     DPLL_CTRL1_OVERRIDE(SKL_DPLL0) |
+		     skl_dpll0_link_rate(dev_priv, vco));
 	intel_de_posting_read(dev_priv, DPLL_CTRL1);
 
-	intel_de_write(dev_priv, LCPLL1_CTL,
-		       intel_de_read(dev_priv, LCPLL1_CTL) | LCPLL_PLL_ENABLE);
+	intel_de_rmw(dev_priv, LCPLL1_CTL,
+		     0, LCPLL_PLL_ENABLE);
 
 	if (intel_de_wait_for_set(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 5))
 		drm_err(&dev_priv->drm, "DPLL0 not locked\n");
@@ -995,8 +991,9 @@ static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
 
 static void skl_dpll0_disable(struct drm_i915_private *dev_priv)
 {
-	intel_de_write(dev_priv, LCPLL1_CTL,
-		       intel_de_read(dev_priv, LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
+	intel_de_rmw(dev_priv, LCPLL1_CTL,
+		     LCPLL_PLL_ENABLE, 0);
+
 	if (intel_de_wait_for_clear(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 1))
 		drm_err(&dev_priv->drm, "Couldn't disable DPLL0\n");
 
-- 
2.26.3

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  parent reply	other threads:[~2021-04-30 15:35 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-30 15:34 [Intel-gfx] [PATCH 0/5] drm/i915: cdclk cleanups Ville Syrjala
2021-04-30 15:34 ` [Intel-gfx] [PATCH 1/5] drm/i915: Extract some helpers to compute cdclk register values Ville Syrjala
2021-04-30 15:34 ` [Intel-gfx] [PATCH 2/5] drm/i915: Use intel_de_rmw() in bdw cdclk programming Ville Syrjala
2021-05-03 17:53   ` Jani Nikula
2021-04-30 15:34 ` Ville Syrjala [this message]
2021-04-30 15:34 ` [Intel-gfx] [PATCH 4/5] drm/i915: Use intel_de_rmw() in bxt/glk/cnl+ " Ville Syrjala
2021-04-30 15:34 ` [Intel-gfx] [PATCH 5/5] drm/i915: Use intel_de_wait_for_*() in cnl+ " Ville Syrjala
2021-05-03 12:46 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: cdclk cleanups Patchwork
2021-05-03 14:47 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-05-03 17:55 ` [Intel-gfx] [PATCH 0/5] " Jani Nikula

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