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From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 5/5] drm/i915: Use intel_de_wait_for_*() in cnl+ cdclk programming
Date: Fri, 30 Apr 2021 18:34:44 +0300	[thread overview]
Message-ID: <20210430153444.29270-6-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20210430153444.29270-1-ville.syrjala@linux.intel.com>

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Replace the hand rolled PLL lock bit waits with intel_de_wait_for_*().

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 10 ++++------
 1 file changed, 4 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index ab68a2d70830..f8ed19205315 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1492,9 +1492,8 @@ static void cnl_cdclk_pll_disable(struct drm_i915_private *dev_priv)
 		     BXT_DE_PLL_PLL_ENABLE, 0);
 
 	/* Timeout 200us */
-	if (wait_for((intel_de_read(dev_priv, BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) == 0, 1))
-		drm_err(&dev_priv->drm,
-			"timeout waiting for CDCLK PLL unlock\n");
+	if (intel_de_wait_for_clear(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
+		drm_err(&dev_priv->drm, "timeout waiting for CDCLK PLL unlock\n");
 
 	dev_priv->cdclk.hw.vco = 0;
 }
@@ -1511,9 +1510,8 @@ static void cnl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco)
 	intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
 
 	/* Timeout 200us */
-	if (wait_for((intel_de_read(dev_priv, BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) != 0, 1))
-		drm_err(&dev_priv->drm,
-			"timeout waiting for CDCLK PLL lock\n");
+	if (intel_de_wait_for_set(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
+		drm_err(&dev_priv->drm, "timeout waiting for CDCLK PLL lock\n");
 
 	dev_priv->cdclk.hw.vco = vco;
 }
-- 
2.26.3

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  parent reply	other threads:[~2021-04-30 15:35 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-30 15:34 [Intel-gfx] [PATCH 0/5] drm/i915: cdclk cleanups Ville Syrjala
2021-04-30 15:34 ` [Intel-gfx] [PATCH 1/5] drm/i915: Extract some helpers to compute cdclk register values Ville Syrjala
2021-04-30 15:34 ` [Intel-gfx] [PATCH 2/5] drm/i915: Use intel_de_rmw() in bdw cdclk programming Ville Syrjala
2021-05-03 17:53   ` Jani Nikula
2021-04-30 15:34 ` [Intel-gfx] [PATCH 3/5] drm/i915: Use intel_de_rmw() in skl " Ville Syrjala
2021-04-30 15:34 ` [Intel-gfx] [PATCH 4/5] drm/i915: Use intel_de_rmw() in bxt/glk/cnl+ " Ville Syrjala
2021-04-30 15:34 ` Ville Syrjala [this message]
2021-05-03 12:46 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: cdclk cleanups Patchwork
2021-05-03 14:47 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-05-03 17:55 ` [Intel-gfx] [PATCH 0/5] " Jani Nikula

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