public inbox for intel-gfx@lists.freedesktop.org
 help / color / mirror / Atom feed
From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 08/14] drm/i915: Simplify up g4x watermark sanitation
Date: Fri, 14 May 2021 15:57:45 +0300	[thread overview]
Message-ID: <20210514125751.17075-9-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20210514125751.17075-1-ville.syrjala@linux.intel.com>

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We can simplify the g4x watermark sanitation by reusing the
second half of g4x_compute_pipe_wm() to convert the sanitized
raw watermarks into the proper form to be used as the
optimal/intermediate watermarks.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 21 +++++++--------------
 1 file changed, 7 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 115cbf4cd10f..b2ebc5ff0007 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6552,37 +6552,30 @@ void g4x_wm_sanitize(struct drm_i915_private *dev_priv)
 			to_intel_crtc_state(crtc->base.state);
 		struct intel_plane_state *plane_state =
 			to_intel_plane_state(plane->base.state);
-		struct g4x_wm_state *wm_state = &crtc_state->wm.g4x.optimal;
 		enum plane_id plane_id = plane->id;
-		int level;
+		int level, num_levels = intel_wm_num_levels(dev_priv);
 
 		if (plane_state->uapi.visible)
 			continue;
 
-		for (level = 0; level < 3; level++) {
+		for (level = 0; level < num_levels; level++) {
 			struct g4x_pipe_wm *raw =
 				&crtc_state->wm.g4x.raw[level];
 
 			raw->plane[plane_id] = 0;
-			wm_state->wm.plane[plane_id] = 0;
-		}
 
-		if (plane_id == PLANE_PRIMARY) {
-			for (level = 0; level < 3; level++) {
-				struct g4x_pipe_wm *raw =
-					&crtc_state->wm.g4x.raw[level];
+			if (plane_id == PLANE_PRIMARY)
 				raw->fbc = 0;
-			}
-
-			wm_state->sr.fbc = 0;
-			wm_state->hpll.fbc = 0;
-			wm_state->fbc_en = false;
 		}
 	}
 
 	for_each_intel_crtc(&dev_priv->drm, crtc) {
 		struct intel_crtc_state *crtc_state =
 			to_intel_crtc_state(crtc->base.state);
+		int ret;
+
+		ret = _g4x_compute_pipe_wm(crtc_state);
+		drm_WARN_ON(&dev_priv->drm, ret);
 
 		crtc_state->wm.g4x.intermediate =
 			crtc_state->wm.g4x.optimal;
-- 
2.26.3

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  parent reply	other threads:[~2021-05-14 12:58 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-14 12:57 [Intel-gfx] [PATCH 00/14] drm/i915: g4x/vlv/chv CxSR/wm fixes/cleanups Ville Syrjala
2021-05-14 12:57 ` [Intel-gfx] [PATCH 01/14] drm/i915: s/crtc_state/new_crtc_state/ etc Ville Syrjala
2021-09-16 16:17   ` Lisovskiy, Stanislav
2021-05-14 12:57 ` [Intel-gfx] [PATCH 02/14] drm/i915: Fix g4x cxsr enable condition Ville Syrjala
2021-09-16 16:24   ` Lisovskiy, Stanislav
2021-09-17 12:32     ` Ville Syrjälä
2021-09-17 15:05       ` Lisovskiy, Stanislav
2021-05-14 12:57 ` [Intel-gfx] [PATCH 03/14] drm/i915: Use u8 consistently for active_planes bitmask Ville Syrjala
2021-09-16 16:43   ` Lisovskiy, Stanislav
2021-05-14 12:57 ` [Intel-gfx] [PATCH 04/14] drm/i915: Apply WaUse32BppForSRWM to elk as well as ctg Ville Syrjala
2021-09-17 15:09   ` Lisovskiy, Stanislav
2021-05-14 12:57 ` [Intel-gfx] [PATCH 05/14] drm/i915: Fix HPLL watermark readout for g4x Ville Syrjala
2021-09-17 15:34   ` Lisovskiy, Stanislav
2021-09-22 14:05     ` Ville Syrjälä
2021-09-23 13:24       ` Lisovskiy, Stanislav
2021-09-23 15:51         ` Ville Syrjälä
2021-05-14 12:57 ` [Intel-gfx] [PATCH 06/14] drm/i915: Split g4x_compute_pipe_wm() into two Ville Syrjala
2021-09-23 18:16   ` Lisovskiy, Stanislav
2021-05-14 12:57 ` [Intel-gfx] [PATCH 07/14] drm/i915: Split vlv_compute_pipe_wm() " Ville Syrjala
2021-05-14 12:57 ` Ville Syrjala [this message]
2021-05-14 12:57 ` [Intel-gfx] [PATCH 09/14] drm/i915: Simplify up vlv watermark sanitation Ville Syrjala
2021-05-14 12:57 ` [Intel-gfx] [PATCH 10/14] drm/i915: Add missing invalidate to g4x wm readout Ville Syrjala
2021-05-14 12:57 ` [Intel-gfx] [PATCH 11/14] drm/i915: Fix g4x/vlv/chv CxSR vs. format/tiling/rotation changes Ville Syrjala
2021-05-14 12:57 ` [Intel-gfx] [PATCH 12/14] drm/i915: Fix pipe gamma enable/disable vs. CxSR on gmch platforms Ville Syrjala
2021-05-14 12:57 ` [Intel-gfx] [PATCH 13/14] drm/i915: Write watermarks for disabled pipes " Ville Syrjala
2021-05-14 12:57 ` [Intel-gfx] [PATCH 14/14] drm/i915: Enable atomic by default on ctg/elk Ville Syrjala
2021-05-14 15:05 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: g4x/vlv/chv CxSR/wm fixes/cleanups Patchwork
2021-05-14 15:33 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-05-14 22:44 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-05-25 16:54 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: g4x/vlv/chv CxSR/wm fixes/cleanups (rev2) Patchwork
2021-05-25 17:25 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-05-25 22:11 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20210514125751.17075-9-ville.syrjala@linux.intel.com \
    --to=ville.syrjala@linux.intel.com \
    --cc=intel-gfx@lists.freedesktop.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox