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From: "Lisovskiy, Stanislav" <stanislav.lisovskiy@intel.com>
To: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 05/14] drm/i915: Fix HPLL watermark readout for g4x
Date: Fri, 17 Sep 2021 18:34:22 +0300	[thread overview]
Message-ID: <20210917153422.GB1224@intel.com> (raw)
In-Reply-To: <20210514125751.17075-6-ville.syrjala@linux.intel.com>

On Fri, May 14, 2021 at 03:57:42PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> If HPLL watermarks are already enabled, let's not mark them as
> disabled by forgetting to bump 'level' before we call
> g4x_raw_plane_wm_set().
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 7 +++++--
>  1 file changed, 5 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 661bc6fdf38c..990ee5a590d3 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -6468,7 +6468,8 @@ void g4x_wm_get_hw_state(struct drm_i915_private *dev_priv)
>  		for_each_plane_id_on_crtc(crtc, plane_id)
>  			raw->plane[plane_id] = active->wm.plane[plane_id];
>  
> -		if (++level > max_level)
> +		level = G4X_WM_LEVEL_SR;
> +		if (level > max_level)

Do I understand correctly that its basically identical to what
was before, so this is done here just for it to look more explicit?

I.e we had for example max_level G4X_WM_LEVEL_SR and level G4X_WM_LEVEL_NORMAL
, after ++level it will anyway become G4X_WM_LEVEL_SR and same for next one.


>  			goto out;
>  
>  		raw = &crtc_state->wm.g4x.raw[level];
> @@ -6477,7 +6478,8 @@ void g4x_wm_get_hw_state(struct drm_i915_private *dev_priv)
>  		raw->plane[PLANE_SPRITE0] = 0;
>  		raw->fbc = active->sr.fbc;
>  
> -		if (++level > max_level)
> +		level = G4X_WM_LEVEL_HPLL;
> +		if (level > max_level)
>  			goto out;
>  
>  		raw = &crtc_state->wm.g4x.raw[level];
> @@ -6486,6 +6488,7 @@ void g4x_wm_get_hw_state(struct drm_i915_private *dev_priv)
>  		raw->plane[PLANE_SPRITE0] = 0;
>  		raw->fbc = active->hpll.fbc;
>  
> +		level++;

Hi Ville,

So if we reached here, it means level = G4X_WM_LEVEL_HPLL, which is 
the max wm level defined, why are we then incrementing it even more?

the g4x_raw_plane_wm_set will be using that value as a level:

for (; level < intel_wm_num_levels(dev_priv); level++) {
	struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];

	dirty |= raw->plane[plane_id] != value;
	raw->plane[plane_id] = value;
}

however level then will be equal to NUM_G4X_WM_LEVELS, which is actually
an illegal value, or is that an expected behaviour?

Just trying to understand, whats happening here, before stamping an r-b :)

Stan


>  	out:
>  		for_each_plane_id_on_crtc(crtc, plane_id)
>  			g4x_raw_plane_wm_set(crtc_state, level,
> -- 
> 2.26.3
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2021-09-17 15:33 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-14 12:57 [Intel-gfx] [PATCH 00/14] drm/i915: g4x/vlv/chv CxSR/wm fixes/cleanups Ville Syrjala
2021-05-14 12:57 ` [Intel-gfx] [PATCH 01/14] drm/i915: s/crtc_state/new_crtc_state/ etc Ville Syrjala
2021-09-16 16:17   ` Lisovskiy, Stanislav
2021-05-14 12:57 ` [Intel-gfx] [PATCH 02/14] drm/i915: Fix g4x cxsr enable condition Ville Syrjala
2021-09-16 16:24   ` Lisovskiy, Stanislav
2021-09-17 12:32     ` Ville Syrjälä
2021-09-17 15:05       ` Lisovskiy, Stanislav
2021-05-14 12:57 ` [Intel-gfx] [PATCH 03/14] drm/i915: Use u8 consistently for active_planes bitmask Ville Syrjala
2021-09-16 16:43   ` Lisovskiy, Stanislav
2021-05-14 12:57 ` [Intel-gfx] [PATCH 04/14] drm/i915: Apply WaUse32BppForSRWM to elk as well as ctg Ville Syrjala
2021-09-17 15:09   ` Lisovskiy, Stanislav
2021-05-14 12:57 ` [Intel-gfx] [PATCH 05/14] drm/i915: Fix HPLL watermark readout for g4x Ville Syrjala
2021-09-17 15:34   ` Lisovskiy, Stanislav [this message]
2021-09-22 14:05     ` Ville Syrjälä
2021-09-23 13:24       ` Lisovskiy, Stanislav
2021-09-23 15:51         ` Ville Syrjälä
2021-05-14 12:57 ` [Intel-gfx] [PATCH 06/14] drm/i915: Split g4x_compute_pipe_wm() into two Ville Syrjala
2021-09-23 18:16   ` Lisovskiy, Stanislav
2021-05-14 12:57 ` [Intel-gfx] [PATCH 07/14] drm/i915: Split vlv_compute_pipe_wm() " Ville Syrjala
2021-05-14 12:57 ` [Intel-gfx] [PATCH 08/14] drm/i915: Simplify up g4x watermark sanitation Ville Syrjala
2021-05-14 12:57 ` [Intel-gfx] [PATCH 09/14] drm/i915: Simplify up vlv " Ville Syrjala
2021-05-14 12:57 ` [Intel-gfx] [PATCH 10/14] drm/i915: Add missing invalidate to g4x wm readout Ville Syrjala
2021-05-14 12:57 ` [Intel-gfx] [PATCH 11/14] drm/i915: Fix g4x/vlv/chv CxSR vs. format/tiling/rotation changes Ville Syrjala
2021-05-14 12:57 ` [Intel-gfx] [PATCH 12/14] drm/i915: Fix pipe gamma enable/disable vs. CxSR on gmch platforms Ville Syrjala
2021-05-14 12:57 ` [Intel-gfx] [PATCH 13/14] drm/i915: Write watermarks for disabled pipes " Ville Syrjala
2021-05-14 12:57 ` [Intel-gfx] [PATCH 14/14] drm/i915: Enable atomic by default on ctg/elk Ville Syrjala
2021-05-14 15:05 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: g4x/vlv/chv CxSR/wm fixes/cleanups Patchwork
2021-05-14 15:33 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-05-14 22:44 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-05-25 16:54 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: g4x/vlv/chv CxSR/wm fixes/cleanups (rev2) Patchwork
2021-05-25 17:25 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-05-25 22:11 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

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