From: "Lisovskiy, Stanislav" <stanislav.lisovskiy@intel.com>
To: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 02/14] drm/i915: Fix g4x cxsr enable condition
Date: Fri, 17 Sep 2021 18:05:16 +0300 [thread overview]
Message-ID: <20210917150516.GA1197@intel.com> (raw)
In-Reply-To: <YUSK83PNOgEPQjB7@intel.com>
On Fri, Sep 17, 2021 at 03:32:51PM +0300, Ville Syrjälä wrote:
> On Thu, Sep 16, 2021 at 07:24:21PM +0300, Lisovskiy, Stanislav wrote:
> > On Fri, May 14, 2021 at 03:57:39PM +0300, Ville Syrjala wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > >
> > > The intention was to check whether the primary plane is enabled
> > > without any sprites planes being enabled. Instead we ended up checking
> > > whether just any one of the planes is enabled. g4x isn't vlv/chv and
> > > cxsr only works with the primary plane. Fix the check to examine the
> > > bitmask of active planes rather than the number of bits set in said
> > > bitmask.
> > >
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > ---
> > > drivers/gpu/drm/i915/intel_pm.c | 5 ++---
> > > 1 file changed, 2 insertions(+), 3 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > index 00a5fe424c5a..2fb496fbed43 100644
> > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > @@ -1376,8 +1376,7 @@ static int g4x_compute_pipe_wm(struct intel_crtc_state *crtc_state)
> > > struct intel_atomic_state *state =
> > > to_intel_atomic_state(crtc_state->uapi.state);
> > > struct g4x_wm_state *wm_state = &crtc_state->wm.g4x.optimal;
> > > - int num_active_planes = hweight8(crtc_state->active_planes &
> > > - ~BIT(PLANE_CURSOR));
> > > + u8 active_planes = crtc_state->active_planes & ~BIT(PLANE_CURSOR);
> > > const struct g4x_pipe_wm *raw;
> > > const struct intel_plane_state *old_plane_state;
> > > const struct intel_plane_state *new_plane_state;
> > > @@ -1417,7 +1416,7 @@ static int g4x_compute_pipe_wm(struct intel_crtc_state *crtc_state)
> > > wm_state->sr.cursor = raw->plane[PLANE_CURSOR];
> > > wm_state->sr.fbc = raw->fbc;
> > >
> > > - wm_state->cxsr = num_active_planes == BIT(PLANE_PRIMARY);
> > > + wm_state->cxsr = active_planes == BIT(PLANE_PRIMARY);
> >
> > Shouldn't this be "active_planes & BIT(PLANE_PRIMARY)" as we might
> > have other non-cursor planes enabled, which will then fail or am I missing something?
>
> CxSR is possible only when the primary plane is enabled and the
> sprite plane is disabled.
Ok, that explains.
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
>
> --
> Ville Syrjälä
> Intel
next prev parent reply other threads:[~2021-09-17 15:04 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-14 12:57 [Intel-gfx] [PATCH 00/14] drm/i915: g4x/vlv/chv CxSR/wm fixes/cleanups Ville Syrjala
2021-05-14 12:57 ` [Intel-gfx] [PATCH 01/14] drm/i915: s/crtc_state/new_crtc_state/ etc Ville Syrjala
2021-09-16 16:17 ` Lisovskiy, Stanislav
2021-05-14 12:57 ` [Intel-gfx] [PATCH 02/14] drm/i915: Fix g4x cxsr enable condition Ville Syrjala
2021-09-16 16:24 ` Lisovskiy, Stanislav
2021-09-17 12:32 ` Ville Syrjälä
2021-09-17 15:05 ` Lisovskiy, Stanislav [this message]
2021-05-14 12:57 ` [Intel-gfx] [PATCH 03/14] drm/i915: Use u8 consistently for active_planes bitmask Ville Syrjala
2021-09-16 16:43 ` Lisovskiy, Stanislav
2021-05-14 12:57 ` [Intel-gfx] [PATCH 04/14] drm/i915: Apply WaUse32BppForSRWM to elk as well as ctg Ville Syrjala
2021-09-17 15:09 ` Lisovskiy, Stanislav
2021-05-14 12:57 ` [Intel-gfx] [PATCH 05/14] drm/i915: Fix HPLL watermark readout for g4x Ville Syrjala
2021-09-17 15:34 ` Lisovskiy, Stanislav
2021-09-22 14:05 ` Ville Syrjälä
2021-09-23 13:24 ` Lisovskiy, Stanislav
2021-09-23 15:51 ` Ville Syrjälä
2021-05-14 12:57 ` [Intel-gfx] [PATCH 06/14] drm/i915: Split g4x_compute_pipe_wm() into two Ville Syrjala
2021-09-23 18:16 ` Lisovskiy, Stanislav
2021-05-14 12:57 ` [Intel-gfx] [PATCH 07/14] drm/i915: Split vlv_compute_pipe_wm() " Ville Syrjala
2021-05-14 12:57 ` [Intel-gfx] [PATCH 08/14] drm/i915: Simplify up g4x watermark sanitation Ville Syrjala
2021-05-14 12:57 ` [Intel-gfx] [PATCH 09/14] drm/i915: Simplify up vlv " Ville Syrjala
2021-05-14 12:57 ` [Intel-gfx] [PATCH 10/14] drm/i915: Add missing invalidate to g4x wm readout Ville Syrjala
2021-05-14 12:57 ` [Intel-gfx] [PATCH 11/14] drm/i915: Fix g4x/vlv/chv CxSR vs. format/tiling/rotation changes Ville Syrjala
2021-05-14 12:57 ` [Intel-gfx] [PATCH 12/14] drm/i915: Fix pipe gamma enable/disable vs. CxSR on gmch platforms Ville Syrjala
2021-05-14 12:57 ` [Intel-gfx] [PATCH 13/14] drm/i915: Write watermarks for disabled pipes " Ville Syrjala
2021-05-14 12:57 ` [Intel-gfx] [PATCH 14/14] drm/i915: Enable atomic by default on ctg/elk Ville Syrjala
2021-05-14 15:05 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: g4x/vlv/chv CxSR/wm fixes/cleanups Patchwork
2021-05-14 15:33 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-05-14 22:44 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-05-25 16:54 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: g4x/vlv/chv CxSR/wm fixes/cleanups (rev2) Patchwork
2021-05-25 17:25 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-05-25 22:11 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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