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From: Uma Shankar <uma.shankar@intel.com>
To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 7/9] drm/i915/xelpd: Enable Pipe Degamma
Date: Tue,  1 Jun 2021 16:11:33 +0530	[thread overview]
Message-ID: <20210601104135.29020-8-uma.shankar@intel.com> (raw)
In-Reply-To: <20210601104135.29020-1-uma.shankar@intel.com>

Enable Pipe Degamma for XE_LPD. Extend the legacy implementation
to incorparate the extended lut size for XE_LPD.

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 18b51b9cc2aa..a8b771f22880 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -829,6 +829,12 @@ static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state)
 	enum pipe pipe = crtc->pipe;
 	int i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
 	const struct drm_color_lut *lut = crtc_state->hw.degamma_lut->data;
+	u32 extended_lut_size = 0;
+
+	if (DISPLAY_VER(dev_priv) >= 13)
+		extended_lut_size = 131;
+	else
+		extended_lut_size = 35;
 
 	/*
 	 * When setting the auto-increment bit, the hardware seems to
@@ -841,8 +847,8 @@ static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state)
 
 	for (i = 0; i < lut_size; i++) {
 		/*
-		 * First 33 entries represent range from 0 to 1.0
-		 * 34th and 35th entry will represent extended range
+		 * First lut_size entries represent range from 0 to 1.0
+		 * 3 additional lut entries will represent extended range
 		 * inputs 3.0 and 7.0 respectively, currently clamped
 		 * at 1.0. Since the precision is 16bit, the user
 		 * value can be directly filled to register.
@@ -858,7 +864,7 @@ static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state)
 	}
 
 	/* Clamp values > 1.0. */
-	while (i++ < 35)
+	while (i++ < extended_lut_size)
 		intel_de_write(dev_priv, PRE_CSC_GAMC_DATA(pipe), 1 << 16);
 
 	intel_de_write(dev_priv, PRE_CSC_GAMC_INDEX(pipe), 0);
-- 
2.26.2

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  parent reply	other threads:[~2021-06-01 10:06 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-01 10:41 [Intel-gfx] [PATCH 0/9] Enhance pipe color support for multi segmented luts Uma Shankar
2021-06-01 10:41 ` [Intel-gfx] [PATCH 1/9] drm: Add gamma mode property Uma Shankar
2021-06-02  9:09   ` Pekka Paalanen
2021-06-02 20:18     ` Shankar, Uma
2021-06-03  8:05       ` Pekka Paalanen
2021-06-01 10:41 ` [Intel-gfx] [PATCH 2/9] drm/i915/xelpd: Define color lut range structure Uma Shankar
2021-06-01 10:41 ` [Intel-gfx] [PATCH 3/9] drm/i915/xelpd: Add support for Logarithmic gamma mode Uma Shankar
2021-06-01 10:41 ` [Intel-gfx] [PATCH 4/9] drm/i915/xelpd: Attach gamma mode property Uma Shankar
2021-06-01 10:41 ` [Intel-gfx] [PATCH 5/9] drm: Add Client Cap for advance gamma mode Uma Shankar
2021-06-02  2:53   ` kernel test robot
2021-06-02  9:03   ` Pekka Paalanen
2021-06-02 20:08     ` Shankar, Uma
2021-06-01 10:41 ` [Intel-gfx] [PATCH 6/9] drm/i915/xelpd: logarithmic gamma enabled only with " Uma Shankar
2021-06-01 10:41 ` Uma Shankar [this message]
2021-06-01 10:41 ` [Intel-gfx] [PATCH 8/9] drm/i915/xelpd: Add Pipe Color Lut caps to platform config Uma Shankar
2021-06-01 10:41 ` [Intel-gfx] [PATCH 9/9] drm/i915/xelpd: Enable XE_LPD Gamma Lut readout Uma Shankar
2021-06-01 12:47 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Enhance pipe color support for multi segmented luts Patchwork
2021-06-01 13:15 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-06-01 17:12 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-06-04 18:51 ` [Intel-gfx] [PATCH 0/9] " Harry Wentland
2021-06-07  7:29   ` Pekka Paalanen
2021-06-07 18:07     ` Shankar, Uma
2021-06-08  7:59       ` Pekka Paalanen
2021-06-07 18:01   ` Shankar, Uma
2021-06-07 21:00     ` Harry Wentland

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