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* [Intel-gfx] [PATCH v2 1/2] drm/i915/gem: only allow WC for lmem
@ 2021-06-25 12:27 Matthew Auld
  2021-06-25 12:27 ` [Intel-gfx] [PATCH v2 2/2] drm/i915/gem: only allow WB for smem only placements Matthew Auld
                   ` (5 more replies)
  0 siblings, 6 replies; 12+ messages in thread
From: Matthew Auld @ 2021-06-25 12:27 UTC (permalink / raw)
  To: intel-gfx; +Cc: Thomas Hellström, dri-devel, Daniel Vetter

This is already the case for our kernel internal mappings, and since we
now only support a single mode this should always be WC if the object
can be placed in lmem.

v2: rebase and also update set_domain

Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/gem/i915_gem_domain.c |  6 ++++++
 drivers/gpu/drm/i915/gem/i915_gem_mman.c   |  9 +++++++++
 drivers/gpu/drm/i915/gem/i915_gem_object.c | 21 +++++++++++++++++++++
 drivers/gpu/drm/i915/gem/i915_gem_object.h |  4 ++++
 4 files changed, 40 insertions(+)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
index 073822100da7..d0c91697bb22 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
@@ -571,6 +571,12 @@ i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
 	if (READ_ONCE(obj->write_domain) == read_domains)
 		goto out_unpin;
 
+	if (i915_gem_object_placements_contain_type(obj, INTEL_MEMORY_LOCAL) &&
+	    read_domains != I915_GEM_DOMAIN_WC) {
+		err = -EINVAL;
+		goto out_unpin;
+	}
+
 	if (read_domains & I915_GEM_DOMAIN_WC)
 		err = i915_gem_object_set_to_wc_domain(obj, write_domain);
 	else if (read_domains & I915_GEM_DOMAIN_GTT)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
index a90f796e85c0..f3586b36dd53 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
@@ -688,6 +688,15 @@ __assign_mmap_offset(struct drm_i915_gem_object *obj,
 	    !i915_gem_object_has_iomem(obj))
 		return -ENODEV;
 
+	/*
+	 * Note that even if the object can also be placed in smem then we still
+	 * map as WC here, since we can only support a single mode. On DG1 this
+	 * sucks since we can't turn off snooping for this case.
+	 */
+	if (mmap_type != I915_MMAP_TYPE_WC &&
+	    i915_gem_object_placements_contain_type(obj, INTEL_MEMORY_LOCAL))
+		return -ENODEV;
+
 	mmo = mmap_offset_attach(obj, mmap_type, file);
 	if (IS_ERR(mmo))
 		return PTR_ERR(mmo);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c b/drivers/gpu/drm/i915/gem/i915_gem_object.c
index 07e8ff9a8aae..326956c18f76 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
@@ -513,6 +513,27 @@ bool i915_gem_object_has_iomem(const struct drm_i915_gem_object *obj)
 	return obj->mem_flags & I915_BO_FLAG_IOMEM;
 }
 
+/**
+ * i915_gem_object_placements_contain_type - Check whether the object can be
+ * placed at certain memory type
+ * @obj: Pointer to the object
+ * @type: The memory type to check
+ *
+ * Return: True if the object can be placed in @type. False otherwise.
+ */
+bool i915_gem_object_placements_contain_type(struct drm_i915_gem_object *obj,
+					     enum intel_memory_type type)
+{
+	unsigned int i;
+
+	for (i = 0; i < obj->mm.n_placements; i++) {
+		if (obj->mm.placements[i]->type == type)
+			return true;
+	}
+
+	return false;
+}
+
 void i915_gem_init__objects(struct drm_i915_private *i915)
 {
 	INIT_WORK(&i915->mm.free_work, __i915_gem_free_work);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h b/drivers/gpu/drm/i915/gem/i915_gem_object.h
index ea3224a480c4..e1daa58bc225 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
@@ -12,6 +12,7 @@
 #include <drm/drm_device.h>
 
 #include "display/intel_frontbuffer.h"
+#include "intel_memory_region.h"
 #include "i915_gem_object_types.h"
 #include "i915_gem_gtt.h"
 #include "i915_gem_ww.h"
@@ -597,6 +598,9 @@ bool i915_gem_object_migratable(struct drm_i915_gem_object *obj);
 
 bool i915_gem_object_validates_to_lmem(struct drm_i915_gem_object *obj);
 
+bool i915_gem_object_placements_contain_type(struct drm_i915_gem_object *obj,
+					     enum intel_memory_type type);
+
 #ifdef CONFIG_MMU_NOTIFIER
 static inline bool
 i915_gem_object_is_userptr(struct drm_i915_gem_object *obj)
-- 
2.26.3

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^ permalink raw reply related	[flat|nested] 12+ messages in thread
end of thread, other threads:[~2021-06-28 10:56 UTC | newest]

Thread overview: 12+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2021-06-25 12:27 [Intel-gfx] [PATCH v2 1/2] drm/i915/gem: only allow WC for lmem Matthew Auld
2021-06-25 12:27 ` [Intel-gfx] [PATCH v2 2/2] drm/i915/gem: only allow WB for smem only placements Matthew Auld
2021-06-28  7:41   ` Thomas Hellström
2021-06-28  9:12     ` Matthew Auld
2021-06-28  9:38       ` Thomas Hellström
2021-06-28 10:20         ` Matthew Auld
2021-06-28 10:55           ` Thomas Hellström
2021-06-25 13:18 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v2,1/2] drm/i915/gem: only allow WC for lmem Patchwork
2021-06-25 13:20 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-06-25 13:49 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-06-25 16:45 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-06-28  7:31 ` [Intel-gfx] [PATCH v2 1/2] " Thomas Hellström

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