From: Matt Atwood <matthew.s.atwood@intel.com>
To: Matt Roper <matthew.d.roper@intel.com>;, intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v2 02/50] drm/i915: Fork DG1 interrupt handler
Date: Mon, 19 Jul 2021 14:18:45 -0700 [thread overview]
Message-ID: <20210719211845.GA18704@msatwood-mobl> (raw)
In-Reply-To: <20210714031540.3539704-3-matthew.d.roper@intel.com>
On Tue, Jul 13, 2021 at 08:14:52PM -0700, Matt Roper wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> The current interrupt handler is getting increasingly complicated and
> Xe_HP changes will bring even more complexity. Let's split off a new
> interrupt handler starting with DG1 (i.e., when the master tile
> interrupt register was added to the design) and use that as the basis
> for the new Xe_HP changes.
>
> Now that we track the hardware IP's release number as well as the
> version number, we can also properly define DG1 has version "12.10" and
> replace the has_master_unit_irq feature flag with an IP version test.
>
> Bspec: 50875
> Cc: Daniele Spurio Ceraolo <daniele.ceraolospurio@intel.com>
> Cc: Stuart Summers <stuart.summers@intel.com>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Tomasz Lis <tomasz.lis@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 -
> drivers/gpu/drm/i915/i915_irq.c | 139 +++++++++++++++--------
> drivers/gpu/drm/i915/i915_pci.c | 2 +-
> drivers/gpu/drm/i915/i915_reg.h | 4 +-
> drivers/gpu/drm/i915/intel_device_info.h | 1 -
> 5 files changed, 95 insertions(+), 53 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index c4747f4407ef..eb7030e5a25b 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1648,8 +1648,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define HAS_LOGICAL_RING_ELSQ(dev_priv) \
> (INTEL_INFO(dev_priv)->has_logical_ring_elsq)
>
> -#define HAS_MASTER_UNIT_IRQ(dev_priv) (INTEL_INFO(dev_priv)->has_master_unit_irq)
> -
> #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
>
> #define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt_type)
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 1d4c683c9de9..61dceb2a17c1 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2698,11 +2698,9 @@ gen11_display_irq_handler(struct drm_i915_private *i915)
> enable_rpm_wakeref_asserts(&i915->runtime_pm);
> }
>
> -static __always_inline irqreturn_t
> -__gen11_irq_handler(struct drm_i915_private * const i915,
> - u32 (*intr_disable)(void __iomem * const regs),
> - void (*intr_enable)(void __iomem * const regs))
> +static irqreturn_t gen11_irq_handler(int irq, void *arg)
> {
> + struct drm_i915_private *i915 = arg;
> void __iomem * const regs = i915->uncore.regs;
> struct intel_gt *gt = &i915->gt;
> u32 master_ctl;
> @@ -2711,9 +2709,9 @@ __gen11_irq_handler(struct drm_i915_private * const i915,
> if (!intel_irqs_enabled(i915))
> return IRQ_NONE;
>
> - master_ctl = intr_disable(regs);
> + master_ctl = gen11_master_intr_disable(regs);
> if (!master_ctl) {
> - intr_enable(regs);
> + gen11_master_intr_enable(regs);
> return IRQ_NONE;
> }
>
> @@ -2726,7 +2724,7 @@ __gen11_irq_handler(struct drm_i915_private * const i915,
>
> gu_misc_iir = gen11_gu_misc_irq_ack(gt, master_ctl);
>
> - intr_enable(regs);
> + gen11_master_intr_enable(regs);
>
> gen11_gu_misc_irq_handler(gt, gu_misc_iir);
>
> @@ -2735,51 +2733,69 @@ __gen11_irq_handler(struct drm_i915_private * const i915,
> return IRQ_HANDLED;
> }
>
> -static irqreturn_t gen11_irq_handler(int irq, void *arg)
> -{
> - return __gen11_irq_handler(arg,
> - gen11_master_intr_disable,
> - gen11_master_intr_enable);
> -}
> -
> -static u32 dg1_master_intr_disable_and_ack(void __iomem * const regs)
> +static inline u32 dg1_master_intr_disable(void __iomem * const regs)
> {
> u32 val;
>
> /* First disable interrupts */
> - raw_reg_write(regs, DG1_MSTR_UNIT_INTR, 0);
> + raw_reg_write(regs, DG1_MSTR_TILE_INTR, 0);
>
> /* Get the indication levels and ack the master unit */
> - val = raw_reg_read(regs, DG1_MSTR_UNIT_INTR);
> + val = raw_reg_read(regs, DG1_MSTR_TILE_INTR);
> if (unlikely(!val))
> return 0;
>
> - raw_reg_write(regs, DG1_MSTR_UNIT_INTR, val);
> -
> - /*
> - * Now with master disabled, get a sample of level indications
> - * for this interrupt and ack them right away - we keep GEN11_MASTER_IRQ
> - * out as this bit doesn't exist anymore for DG1
> - */
> - val = raw_reg_read(regs, GEN11_GFX_MSTR_IRQ) & ~GEN11_MASTER_IRQ;
> - if (unlikely(!val))
> - return 0;
> -
> - raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, val);
> + raw_reg_write(regs, DG1_MSTR_TILE_INTR, val);
>
> return val;
> }
>
> static inline void dg1_master_intr_enable(void __iomem * const regs)
> {
> - raw_reg_write(regs, DG1_MSTR_UNIT_INTR, DG1_MSTR_IRQ);
> + raw_reg_write(regs, DG1_MSTR_TILE_INTR, DG1_MSTR_IRQ);
> }
>
> static irqreturn_t dg1_irq_handler(int irq, void *arg)
> {
> - return __gen11_irq_handler(arg,
> - dg1_master_intr_disable_and_ack,
> - dg1_master_intr_enable);
> + struct drm_i915_private * const i915 = arg;
> + struct intel_gt *gt = &i915->gt;
> + void __iomem * const regs = i915->uncore.regs;
> + u32 master_tile_ctl, master_ctl;
> + u32 gu_misc_iir;
> +
> + if (!intel_irqs_enabled(i915))
> + return IRQ_NONE;
> +
> + master_tile_ctl = dg1_master_intr_disable(regs);
> + if (!master_tile_ctl) {
> + dg1_master_intr_enable(regs);
> + return IRQ_NONE;
> + }
> +
> + /* FIXME: we only support tile 0 for now. */
> + if (master_tile_ctl & DG1_MSTR_TILE(0)) {
> + master_ctl = raw_reg_read(regs, GEN11_GFX_MSTR_IRQ);
> + raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, master_ctl);
> + } else {
> + DRM_ERROR("Tile not supported: 0x%08x\n", master_tile_ctl);
> + dg1_master_intr_enable(regs);
> + return IRQ_NONE;
> + }
> +
> + gen11_gt_irq_handler(gt, master_ctl);
> +
> + if (master_ctl & GEN11_DISPLAY_IRQ)
> + gen11_display_irq_handler(i915);
> +
> + gu_misc_iir = gen11_gu_misc_irq_ack(gt, master_ctl);
> +
> + dg1_master_intr_enable(regs);
> +
> + gen11_gu_misc_irq_handler(gt, gu_misc_iir);
> +
> + pmu_irq_stats(i915, IRQ_HANDLED);
> +
> + return IRQ_HANDLED;
> }
>
> /* Called from drm generic code, passed 'crtc' which
> @@ -3167,10 +3183,20 @@ static void gen11_irq_reset(struct drm_i915_private *dev_priv)
> {
> struct intel_uncore *uncore = &dev_priv->uncore;
>
> - if (HAS_MASTER_UNIT_IRQ(dev_priv))
> - dg1_master_intr_disable_and_ack(dev_priv->uncore.regs);
> - else
> - gen11_master_intr_disable(dev_priv->uncore.regs);
> + gen11_master_intr_disable(dev_priv->uncore.regs);
> +
> + gen11_gt_irq_reset(&dev_priv->gt);
> + gen11_display_irq_reset(dev_priv);
> +
> + GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_);
> + GEN3_IRQ_RESET(uncore, GEN8_PCU_);
> +}
> +
> +static void dg1_irq_reset(struct drm_i915_private *dev_priv)
> +{
> + struct intel_uncore *uncore = &dev_priv->uncore;
> +
> + dg1_master_intr_disable(dev_priv->uncore.regs);
>
> gen11_gt_irq_reset(&dev_priv->gt);
> gen11_display_irq_reset(dev_priv);
> @@ -3862,13 +3888,28 @@ static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
>
> GEN3_IRQ_INIT(uncore, GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked);
>
> - if (HAS_MASTER_UNIT_IRQ(dev_priv)) {
> - dg1_master_intr_enable(uncore->regs);
> - intel_uncore_posting_read(&dev_priv->uncore, DG1_MSTR_UNIT_INTR);
> - } else {
> - gen11_master_intr_enable(uncore->regs);
> - intel_uncore_posting_read(&dev_priv->uncore, GEN11_GFX_MSTR_IRQ);
> + gen11_master_intr_enable(uncore->regs);
> + intel_uncore_posting_read(&dev_priv->uncore, GEN11_GFX_MSTR_IRQ);
> +}
> +
> +static void dg1_irq_postinstall(struct drm_i915_private *dev_priv)
> +{
> + struct intel_uncore *uncore = &dev_priv->uncore;
> + u32 gu_misc_masked = GEN11_GU_MISC_GSE;
> +
> + gen11_gt_irq_postinstall(&dev_priv->gt);
> +
> + GEN3_IRQ_INIT(uncore, GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked);
> +
> + if (HAS_DISPLAY(dev_priv)) {
> + icp_irq_postinstall(dev_priv);
> + gen8_de_irq_postinstall(dev_priv);
> + intel_uncore_write(&dev_priv->uncore, GEN11_DISPLAY_INT_CTL,
> + GEN11_DISPLAY_IRQ_ENABLE);
> }
> +
> + dg1_master_intr_enable(dev_priv->uncore.regs);
> + intel_uncore_posting_read(&dev_priv->uncore, DG1_MSTR_TILE_INTR);
> }
>
> static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv)
> @@ -4407,9 +4448,9 @@ static irq_handler_t intel_irq_handler(struct drm_i915_private *dev_priv)
> else
> return i8xx_irq_handler;
> } else {
> - if (HAS_MASTER_UNIT_IRQ(dev_priv))
> + if (GRAPHICS_VER_FULL(dev_priv) >= IP_VER(12, 10))
> return dg1_irq_handler;
> - if (GRAPHICS_VER(dev_priv) >= 11)
> + else if (GRAPHICS_VER(dev_priv) >= 11)
> return gen11_irq_handler;
> else if (GRAPHICS_VER(dev_priv) >= 8)
> return gen8_irq_handler;
> @@ -4432,7 +4473,9 @@ static void intel_irq_reset(struct drm_i915_private *dev_priv)
> else
> i8xx_irq_reset(dev_priv);
> } else {
> - if (GRAPHICS_VER(dev_priv) >= 11)
> + if (GRAPHICS_VER_FULL(dev_priv) >= IP_VER(12, 10))
> + dg1_irq_reset(dev_priv);
> + else if (GRAPHICS_VER(dev_priv) >= 11)
> gen11_irq_reset(dev_priv);
> else if (GRAPHICS_VER(dev_priv) >= 8)
> gen8_irq_reset(dev_priv);
> @@ -4455,7 +4498,9 @@ static void intel_irq_postinstall(struct drm_i915_private *dev_priv)
> else
> i8xx_irq_postinstall(dev_priv);
> } else {
> - if (GRAPHICS_VER(dev_priv) >= 11)
> + if (GRAPHICS_VER_FULL(dev_priv) >= IP_VER(12, 10))
> + dg1_irq_postinstall(dev_priv);
> + else if (GRAPHICS_VER(dev_priv) >= 11)
> gen11_irq_postinstall(dev_priv);
> else if (GRAPHICS_VER(dev_priv) >= 8)
> gen8_irq_postinstall(dev_priv);
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index be5ee5e0e324..060abebdf4a4 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -907,7 +907,6 @@ static const struct intel_device_info rkl_info = {
>
> #define DGFX_FEATURES \
> .memory_regions = REGION_SMEM | REGION_LMEM | REGION_STOLEN_LMEM, \
> - .has_master_unit_irq = 1, \
> .has_llc = 0, \
> .has_snoop = 1, \
> .is_dgfx = 1
> @@ -915,6 +914,7 @@ static const struct intel_device_info rkl_info = {
> static const struct intel_device_info dg1_info __maybe_unused = {
> GEN12_FEATURES,
> DGFX_FEATURES,
> + .graphics_rel = 10,
> PLATFORM(INTEL_DG1),
> .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
> .require_force_probe = 1,
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 943fe485c662..2274e9c01d61 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7985,9 +7985,9 @@ enum {
> #define GEN11_GT_DW1_IRQ (1 << 1)
> #define GEN11_GT_DW0_IRQ (1 << 0)
>
> -#define DG1_MSTR_UNIT_INTR _MMIO(0x190008)
> +#define DG1_MSTR_TILE_INTR _MMIO(0x190008)
> #define DG1_MSTR_IRQ REG_BIT(31)
> -#define DG1_MSTR_UNIT(u) REG_BIT(u)
> +#define DG1_MSTR_TILE(t) REG_BIT(t)
>
> #define GEN11_DISPLAY_INT_CTL _MMIO(0x44200)
> #define GEN11_DISPLAY_IRQ_ENABLE (1 << 31)
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index bd83004c78b6..ba7483acc3f7 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -127,7 +127,6 @@ enum intel_ppgtt_type {
> func(has_llc); \
> func(has_logical_ring_contexts); \
> func(has_logical_ring_elsq); \
> - func(has_master_unit_irq); \
> func(has_pooled_eu); \
> func(has_rc6); \
> func(has_rc6p); \
> --
> 2.25.4
>
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
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next prev parent reply other threads:[~2021-07-19 21:18 UTC|newest]
Thread overview: 88+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-14 3:14 [Intel-gfx] [PATCH v2 00/50] Begin enabling Xe_HP SDV and DG2 platforms Matt Roper
2021-07-14 3:14 ` [Intel-gfx] [PATCH v2 01/50] drm/i915: Add XE_HP initial definitions Matt Roper
2021-07-19 18:05 ` Souza, Jose
2021-07-14 3:14 ` [Intel-gfx] [PATCH v2 02/50] drm/i915: Fork DG1 interrupt handler Matt Roper
2021-07-19 21:18 ` Matt Atwood [this message]
2021-07-14 3:14 ` [Intel-gfx] [PATCH v2 03/50] drm/i915/xehp: VDBOX/VEBOX fusing registers are enable-based Matt Roper
2021-07-19 21:20 ` Matt Atwood
2021-07-14 3:14 ` [Intel-gfx] [PATCH v2 04/50] drm/i915/gen12: Use fuse info to enable SFC Matt Roper
2021-07-14 3:14 ` [Intel-gfx] [PATCH v2 05/50] drm/i915/selftests: Allow for larger engine counts Matt Roper
2021-07-14 3:14 ` [Intel-gfx] [PATCH v2 06/50] drm/i915/xehp: Extra media engines - Part 1 (engine definitions) Matt Roper
2021-07-20 23:03 ` Lucas De Marchi
2021-07-20 23:40 ` John Harrison
2021-07-20 23:49 ` Lucas De Marchi
2021-07-21 18:23 ` Lucas De Marchi
2021-07-14 3:14 ` [Intel-gfx] [PATCH v2 07/50] drm/i915/xehp: Extra media engines - Part 2 (interrupts) Matt Roper
2021-07-14 3:14 ` [Intel-gfx] [PATCH v2 08/50] drm/i915/xehp: Extra media engines - Part 3 (reset) Matt Roper
2021-07-19 18:13 ` Souza, Jose
2021-07-20 20:39 ` Matt Atwood
2021-07-14 3:14 ` [Intel-gfx] [PATCH v2 09/50] drm/i915/xehp: Xe_HP forcewake support Matt Roper
2021-07-20 20:57 ` Matt Atwood
2021-07-14 3:15 ` [Intel-gfx] [PATCH v2 10/50] drm/i915/xehp: Define multicast register ranges Matt Roper
2021-07-19 18:19 ` Souza, Jose
2021-07-14 3:15 ` [Intel-gfx] [PATCH v2 11/50] drm/i915/xehp: Handle new device context ID format Matt Roper
2021-07-20 21:39 ` Matt Atwood
2021-07-14 3:15 ` [Intel-gfx] [PATCH v2 12/50] drm/i915/xehp: New engine context offsets Matt Roper
2021-07-20 22:06 ` Matt Atwood
2021-07-14 3:15 ` [Intel-gfx] [PATCH v2 13/50] drm/i915/xehp: handle new steering options Matt Roper
2021-07-14 3:15 ` [Intel-gfx] [PATCH v2 14/50] drm/i915/xehp: Loop over all gslices for INSTDONE processing Matt Roper
2021-07-14 3:15 ` [Intel-gfx] [PATCH v2 15/50] drm/i915/xehpsdv: add initial XeHP SDV definitions Matt Roper
2021-07-19 18:20 ` Souza, Jose
2021-07-14 3:15 ` [Intel-gfx] [PATCH v2 16/50] drm/i915/xehp: Changes to ss/eu definitions Matt Roper
2021-07-14 3:15 ` [Intel-gfx] [PATCH v2 17/50] drm/i915/xehpsdv: Add maximum sseu limits Matt Roper
2021-07-18 13:10 ` Yokoyama, Caz
2021-07-14 3:15 ` [Intel-gfx] [PATCH v2 18/50] drm/i915/xehpsdv: Add compute DSS type Matt Roper
2021-07-14 3:15 ` [Intel-gfx] [PATCH v2 19/50] drm/i915/xehpsdv: Define steering tables Matt Roper
2021-07-14 3:15 ` [Intel-gfx] [PATCH v2 20/50] drm/i915/xehpsdv: Define MOCS table for XeHP SDV Matt Roper
2021-07-14 3:15 ` [Intel-gfx] [PATCH v2 21/50] drm/i915/xehpsdv: factor out function to read RP_STATE_CAP Matt Roper
2021-07-14 3:15 ` [Intel-gfx] [PATCH v2 22/50] drm/i915/xehpsdv: Read correct RP_STATE_CAP register Matt Roper
2021-07-14 3:15 ` [Intel-gfx] [PATCH v2 23/50] drm/i915/dg2: add DG2 platform info Matt Roper
2021-07-19 18:21 ` Souza, Jose
2021-07-14 3:15 ` [Intel-gfx] [PATCH v2 24/50] drm/i915/dg2: DG2 uses the same sseu limits as XeHP SDV Matt Roper
2021-07-16 16:06 ` Yokoyama, Caz
2021-07-19 18:22 ` Souza, Jose
2021-07-14 3:15 ` [Intel-gfx] [PATCH v2 25/50] drm/i915/dg2: Add forcewake table Matt Roper
2021-07-14 3:15 ` [Intel-gfx] [PATCH v2 26/50] drm/i915/dg2: Update LNCF steering ranges Matt Roper
2021-07-14 3:15 ` [Intel-gfx] [PATCH v2 27/50] drm/i915/dg2: Add SQIDI steering Matt Roper
2021-07-14 3:15 ` [Intel-gfx] [PATCH v2 28/50] drm/i915/dg2: Add new LRI reg offsets Matt Roper
2021-07-14 3:15 ` [Intel-gfx] [PATCH v2 29/50] drm/i915/dg2: Maintain backward-compatible nested batch behavior Matt Roper
2021-07-14 3:15 ` [Intel-gfx] [PATCH v2 30/50] drm/i915/dg2: Report INSTDONE_GEOM values in error state Matt Roper
2021-07-14 3:15 ` [Intel-gfx] [PATCH v2 31/50] drm/i915/dg2: Define MOCS table for DG2 Matt Roper
2021-07-14 3:15 ` [Intel-gfx] [PATCH v2 32/50] drm/i915/dg2: Add fake PCH Matt Roper
2021-07-16 19:52 ` Souza, Jose
2021-07-14 3:15 ` [Intel-gfx] [PATCH v2 33/50] drm/i915/dg2: Add cdclk table and reference clock Matt Roper
2021-07-16 19:36 ` Souza, Jose
2021-07-14 3:15 ` [Intel-gfx] [PATCH v2 34/50] drm/i915/dg2: Skip shared DPLL handling Matt Roper
2021-07-16 19:38 ` Souza, Jose
2021-07-14 3:15 ` [Intel-gfx] [PATCH v2 35/50] drm/i915/dg2: Don't wait for AUX power well enable ACKs Matt Roper
2021-07-16 19:40 ` Souza, Jose
2021-07-14 3:15 ` [Intel-gfx] [PATCH v2 36/50] drm/i915/dg2: Setup display outputs Matt Roper
2021-07-16 19:40 ` Souza, Jose
2021-07-14 3:15 ` [Intel-gfx] [PATCH v2 37/50] drm/i915/dg2: Add dbuf programming Matt Roper
2021-07-16 19:45 ` Souza, Jose
2021-07-14 3:15 ` [Intel-gfx] [PATCH v2 38/50] drm/i915/dg2: Don't program BW_BUDDY registers Matt Roper
2021-07-16 19:47 ` Souza, Jose
2021-07-14 3:15 ` [Intel-gfx] [PATCH v2 39/50] drm/i915/dg2: Don't read DRAM info Matt Roper
2021-07-15 17:17 ` Srivatsa, Anusha
2021-07-14 3:15 ` [Intel-gfx] [PATCH v2 40/50] drm/i915/dg2: DG2 has fixed memory bandwidth Matt Roper
2021-07-21 17:42 ` Srivatsa, Anusha
2021-07-14 3:15 ` [Intel-gfx] [PATCH v2 41/50] drm/i915/dg2: Add MPLLB programming for SNPS PHY Matt Roper
2021-07-14 3:15 ` [Intel-gfx] [PATCH v2 42/50] drm/i915/dg2: Add MPLLB programming for HDMI Matt Roper
2021-07-16 21:13 ` Matt Atwood
2021-07-14 3:15 ` [Intel-gfx] [PATCH v2 43/50] drm/i915/dg2: Add vswing programming for SNPS phys Matt Roper
2021-07-16 21:38 ` Matt Atwood
2021-07-14 3:15 ` [Intel-gfx] [PATCH v2 44/50] drm/i915/dg2: Update modeset sequences Matt Roper
2021-07-14 3:15 ` [Intel-gfx] [PATCH v2 45/50] drm/i915/dg2: Classify DG2 PHY types Matt Roper
2021-07-16 20:50 ` Matt Atwood
2021-07-14 3:15 ` [Intel-gfx] [PATCH v2 46/50] drm/i915/dg2: Wait for SNPS PHY calibration during display init Matt Roper
2021-07-16 20:52 ` Matt Atwood
2021-07-14 3:15 ` [Intel-gfx] [PATCH v2 47/50] drm/i915/dg2: Update lane disable power state during PSR Matt Roper
2021-07-21 17:55 ` Srivatsa, Anusha
2021-07-14 3:15 ` [Intel-gfx] [PATCH v2 48/50] drm/i915/dg2: Add DG2 to the PSR2 defeature list Matt Roper
2021-07-21 17:56 ` Srivatsa, Anusha
2021-07-14 3:15 ` [Intel-gfx] [PATCH v2 49/50] drm/i915/dg2: Update to bigjoiner path Matt Roper
2021-07-14 3:15 ` [Intel-gfx] [PATCH v2 50/50] drm/i915/dg2: Configure PCON in DP pre-enable path Matt Roper
2021-07-14 4:23 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Begin enabling Xe_HP SDV and DG2 platforms (rev5) Patchwork
2021-07-14 4:24 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-07-14 4:51 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-07-14 15:12 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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