From: Matthew Brost <matthew.brost@intel.com>
To: <intel-gfx@lists.freedesktop.org>, <dri-devel@lists.freedesktop.org>
Subject: [Intel-gfx] [PATCH 42/46] drm/i915: Hold all parallel requests until last request, properly handle error
Date: Tue, 3 Aug 2021 15:29:39 -0700 [thread overview]
Message-ID: <20210803222943.27686-43-matthew.brost@intel.com> (raw)
In-Reply-To: <20210803222943.27686-1-matthew.brost@intel.com>
Hold all parallel requests, via a submit fence, until the last request
is generated. If an error occurs in the middle of generating the
requests, skip the requests signal the backend of the error via a
request flag.
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c | 40 +++++++++++++++++--
drivers/gpu/drm/i915/i915_request.h | 9 +++++
2 files changed, 45 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 70784779872a..64af5c704ca7 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -3351,7 +3351,12 @@ i915_gem_do_execbuffer(struct drm_device *dev,
}
if (out_fence) {
- /* Move ownership to caller (i915_gem_execbuffer2_ioctl) */
+ /*
+ * Move ownership to caller (i915_gem_execbuffer2_ioctl), this
+ * must be done before anything in this function can jump to the
+ * 'err_request' label so the caller can safely cleanup any
+ * errors.
+ */
out_fence[batch_number] = dma_fence_get(&eb.request->fence);
/*
@@ -3402,10 +3407,21 @@ i915_gem_do_execbuffer(struct drm_device *dev,
err = eb_submit(&eb, batch, first, last);
err_request:
- if (last)
+ if (last || err)
set_bit(I915_FENCE_FLAG_SUBMIT_PARALLEL,
&eb.request->fence.flags);
+ /*
+ * If the execbuf IOCTL is generating more than 1 request, we hold all
+ * the requests until the last request has been generated in case any of
+ * the requests hit an error. If an error is hit the caller is
+ * responsible for flaging all the requests generated with an error. The
+ * caller is always responsible for releasing the fence on the first
+ * request.
+ */
+ if (intel_context_is_parallel(eb.context) && first)
+ i915_sw_fence_await(&eb.request->submit);
+
i915_request_get(eb.request);
err = eb_request_add(&eb, err);
@@ -3498,7 +3514,7 @@ i915_gem_execbuffer2_ioctl(struct drm_device *dev, void *data,
struct i915_gem_context *ctx;
struct i915_gem_ww_ctx ww;
struct intel_context *parent = NULL;
- unsigned int num_batches = 1, i;
+ unsigned int num_batches = 1, i = 0, j;
bool is_parallel = false;
if (!check_buffer_count(count)) {
@@ -3637,8 +3653,24 @@ i915_gem_execbuffer2_ioctl(struct drm_device *dev, void *data,
out_fences,
&ww);
- if (is_parallel)
+ if (is_parallel) {
+ /*
+ * Mark all requests generated with an error if any of the
+ * requests encountered an error.
+ */
+ for (j = 0; err && j < i; ++j)
+ if (out_fences[j]) {
+ __i915_request_skip(to_request(out_fences[j]));
+ set_bit(I915_FENCE_FLAG_SKIP_PARALLEL,
+ &out_fences[j]->flags);
+ }
+
+ /* Release fence on first request generated */
+ if (out_fences[0])
+ i915_sw_fence_complete(&to_request(out_fences[0])->submit);
+
mutex_unlock(&parent->parallel_submit);
+ }
/*
* Now that we have begun execution of the batchbuffer, we ignore
diff --git a/drivers/gpu/drm/i915/i915_request.h b/drivers/gpu/drm/i915/i915_request.h
index d6d5bf0a5eb5..7f3f66ddf21b 100644
--- a/drivers/gpu/drm/i915/i915_request.h
+++ b/drivers/gpu/drm/i915/i915_request.h
@@ -153,6 +153,15 @@ enum {
* tail.
*/
I915_FENCE_FLAG_SUBMIT_PARALLEL,
+
+ /*
+ * I915_FENCE_FLAG_SKIP_PARALLEL - request with a context in a
+ * parent-child relationship (parallel submission, multi-lrc) that
+ * hit an error while generating requests in the execbuf IOCTL.
+ * Indicates this request should be skipped as another request in
+ * submission / relationship encoutered an error.
+ */
+ I915_FENCE_FLAG_SKIP_PARALLEL,
};
/**
--
2.28.0
next prev parent reply other threads:[~2021-08-03 22:13 UTC|newest]
Thread overview: 111+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-03 22:28 [Intel-gfx] [PATCH 00/46] Parallel submission aka multi-bb execbuf Matthew Brost
2021-08-03 22:28 ` [Intel-gfx] [PATCH 01/46] drm/i915/guc: Allow flexible number of context ids Matthew Brost
2021-08-03 22:28 ` [Intel-gfx] [PATCH 02/46] drm/i915/guc: Connect the number of guc_ids to debugfs Matthew Brost
2021-08-03 22:29 ` [Intel-gfx] [PATCH 03/46] drm/i915/guc: Don't return -EAGAIN to user when guc_ids exhausted Matthew Brost
2021-08-05 8:27 ` Daniel Vetter
2021-08-03 22:29 ` [Intel-gfx] [PATCH 04/46] drm/i915/guc: Don't allow requests not ready to consume all guc_ids Matthew Brost
2021-08-05 8:29 ` Daniel Vetter
2021-08-03 22:29 ` [Intel-gfx] [PATCH 05/46] drm/i915/guc: Introduce guc_submit_engine object Matthew Brost
2021-08-03 22:29 ` [Intel-gfx] [PATCH 06/46] drm/i915/guc: Check return of __xa_store when registering a context Matthew Brost
2021-08-03 22:29 ` [Intel-gfx] [PATCH 07/46] drm/i915/guc: Non-static lrc descriptor registration buffer Matthew Brost
2021-08-03 22:29 ` [Intel-gfx] [PATCH 08/46] drm/i915/guc: Take GT PM ref when deregistering context Matthew Brost
2021-08-03 22:29 ` [Intel-gfx] [PATCH 09/46] drm/i915: Add GT PM unpark worker Matthew Brost
2021-08-03 22:29 ` [Intel-gfx] [PATCH 10/46] drm/i915/guc: Take engine PM when a context is pinned with GuC submission Matthew Brost
2021-08-09 14:23 ` Daniel Vetter
2021-08-09 18:11 ` Matthew Brost
2021-08-10 6:43 ` Daniel Vetter
2021-08-10 21:29 ` Matthew Brost
2021-08-03 22:29 ` [Intel-gfx] [PATCH 11/46] drm/i915/guc: Don't call switch_to_kernel_context " Matthew Brost
2021-08-09 14:27 ` Daniel Vetter
2021-08-09 18:20 ` Matthew Brost
2021-08-10 6:47 ` Daniel Vetter
2021-08-11 17:47 ` Matthew Brost
2021-08-03 22:29 ` [Intel-gfx] [PATCH 12/46] drm/i915/guc: Selftest for GuC flow control Matthew Brost
2021-08-03 22:29 ` [Intel-gfx] [PATCH 13/46] drm/i915: Add logical engine mapping Matthew Brost
2021-08-09 14:28 ` Daniel Vetter
2021-08-09 18:28 ` Matthew Brost
2021-08-10 6:49 ` Daniel Vetter
2021-08-03 22:29 ` [Intel-gfx] [PATCH 14/46] drm/i915: Expose logical engine instance to user Matthew Brost
2021-08-09 14:30 ` Daniel Vetter
2021-08-09 18:37 ` Matthew Brost
2021-08-10 6:53 ` Daniel Vetter
2021-08-11 17:55 ` Matthew Brost
2021-08-03 22:29 ` [Intel-gfx] [PATCH 15/46] drm/i915/guc: Introduce context parent-child relationship Matthew Brost
2021-08-09 14:37 ` Daniel Vetter
2021-08-09 14:40 ` Daniel Vetter
2021-08-09 18:45 ` Matthew Brost
2021-08-09 18:44 ` Matthew Brost
2021-08-10 8:45 ` Daniel Vetter
2021-08-03 22:29 ` [Intel-gfx] [PATCH 16/46] drm/i915/guc: Implement GuC parent-child context pin / unpin functions Matthew Brost
2021-08-09 15:17 ` Daniel Vetter
2021-08-09 18:58 ` Matthew Brost
2021-08-10 8:53 ` Daniel Vetter
2021-08-10 9:07 ` Daniel Vetter
2021-08-11 18:06 ` Matthew Brost
2021-08-12 14:45 ` Daniel Vetter
2021-08-12 14:52 ` Daniel Vetter
2021-08-11 18:23 ` Matthew Brost
2021-08-03 22:29 ` [Intel-gfx] [PATCH 17/46] drm/i915/guc: Add multi-lrc context registration Matthew Brost
2021-08-03 22:29 ` [Intel-gfx] [PATCH 18/46] drm/i915/guc: Ensure GuC schedule operations do not operate on child contexts Matthew Brost
2021-08-03 22:29 ` [Intel-gfx] [PATCH 19/46] drm/i915/guc: Assign contexts in parent-child relationship consecutive guc_ids Matthew Brost
2021-08-09 15:31 ` Daniel Vetter
2021-08-09 19:03 ` Matthew Brost
2021-08-10 9:12 ` Daniel Vetter
2021-08-03 22:29 ` [Intel-gfx] [PATCH 20/46] drm/i915/guc: Add hang check to GuC submit engine Matthew Brost
2021-08-09 15:35 ` Daniel Vetter
2021-08-09 19:05 ` Matthew Brost
2021-08-10 9:18 ` Daniel Vetter
2021-08-03 22:29 ` [Intel-gfx] [PATCH 21/46] drm/i915/guc: Add guc_child_context_destroy Matthew Brost
2021-08-09 15:36 ` Daniel Vetter
2021-08-09 19:06 ` Matthew Brost
2021-08-03 22:29 ` [Intel-gfx] [PATCH 22/46] drm/i915/guc: Implement multi-lrc submission Matthew Brost
2021-08-03 22:29 ` [Intel-gfx] [PATCH 23/46] drm/i915/guc: Insert submit fences between requests in parent-child relationship Matthew Brost
2021-08-09 16:32 ` Daniel Vetter
2021-08-09 16:39 ` Matthew Brost
2021-08-09 17:03 ` Daniel Vetter
2021-08-03 22:29 ` [Intel-gfx] [PATCH 24/46] drm/i915/guc: Implement multi-lrc reset Matthew Brost
2021-08-03 22:29 ` [Intel-gfx] [PATCH 25/46] drm/i915/guc: Update debugfs for GuC multi-lrc Matthew Brost
2021-08-09 16:36 ` Daniel Vetter
2021-08-09 19:13 ` Matthew Brost
2021-08-10 9:23 ` Daniel Vetter
2021-08-10 9:27 ` Daniel Vetter
2021-08-10 17:29 ` Matthew Brost
2021-08-11 10:04 ` Daniel Vetter
2021-08-11 17:35 ` Matthew Brost
2021-08-03 22:29 ` [Intel-gfx] [PATCH 26/46] drm/i915: Connect UAPI to GuC multi-lrc interface Matthew Brost
2021-08-09 16:37 ` Daniel Vetter
2021-08-03 22:29 ` [Intel-gfx] [PATCH 27/46] drm/i915/doc: Update parallel submit doc to point to i915_drm.h Matthew Brost
2021-08-03 22:29 ` [Intel-gfx] [PATCH 28/46] drm/i915/guc: Add basic GuC multi-lrc selftest Matthew Brost
2021-08-03 22:29 ` [Intel-gfx] [PATCH 29/46] drm/i915/guc: Extend GuC flow control selftest for multi-lrc Matthew Brost
2021-08-03 22:29 ` [Intel-gfx] [PATCH 30/46] drm/i915/guc: Implement no mid batch preemption " Matthew Brost
2021-08-03 22:29 ` [Intel-gfx] [PATCH 31/46] drm/i915: Move secure execbuf check to execbuf2 Matthew Brost
2021-08-03 22:29 ` [Intel-gfx] [PATCH 32/46] drm/i915: Move input/exec fence handling to i915_gem_execbuffer2 Matthew Brost
2021-08-03 22:29 ` [Intel-gfx] [PATCH 33/46] drm/i915: Move output " Matthew Brost
2021-08-03 22:29 ` [Intel-gfx] [PATCH 34/46] drm/i915: Return output fence from i915_gem_do_execbuffer Matthew Brost
2021-08-03 22:29 ` [Intel-gfx] [PATCH 35/46] drm/i915: Store batch index in struct i915_execbuffer Matthew Brost
2021-08-03 22:29 ` [Intel-gfx] [PATCH 36/46] drm/i915: Allow callers of i915_gem_do_execbuffer to override the batch index Matthew Brost
2021-08-03 22:29 ` [Intel-gfx] [PATCH 37/46] drm/i915: Teach execbuf there can be more than one batch in the objects list Matthew Brost
2021-08-03 22:29 ` [Intel-gfx] [PATCH 38/46] drm/i915: Only track object dependencies on first request Matthew Brost
2021-08-03 22:29 ` [Intel-gfx] [PATCH 39/46] drm/i915: Force parallel contexts to use copy engine for reloc Matthew Brost
2021-08-09 16:39 ` Daniel Vetter
2021-08-03 22:29 ` [Intel-gfx] [PATCH 40/46] drm/i915: Multi-batch execbuffer2 Matthew Brost
2021-08-09 17:02 ` Daniel Vetter
2021-08-03 22:29 ` [Intel-gfx] [PATCH 41/46] drm/i915: Eliminate unnecessary VMA calls for multi-BB submission Matthew Brost
2021-08-09 17:07 ` Daniel Vetter
2021-08-09 17:12 ` Daniel Vetter
2021-08-03 22:29 ` Matthew Brost [this message]
2021-08-03 22:29 ` [Intel-gfx] [PATCH 43/46] drm/i915/guc: Handle errors in multi-lrc requests Matthew Brost
2021-08-03 22:29 ` [Intel-gfx] [PATCH 44/46] drm/i915: Enable multi-bb execbuf Matthew Brost
2021-08-03 22:29 ` [Intel-gfx] [PATCH 45/46] drm/i915/execlists: Weak parallel submission support for execlists Matthew Brost
2021-08-03 22:29 ` [Intel-gfx] [PATCH 46/46] drm/i915/guc: Add delay before disabling scheduling on contexts Matthew Brost
2021-08-09 17:17 ` Daniel Vetter
2021-08-09 19:32 ` Matthew Brost
2021-08-11 9:55 ` Daniel Vetter
2021-08-11 17:43 ` Matthew Brost
2021-08-12 14:04 ` Daniel Vetter
2021-08-12 19:26 ` Daniel Vetter
2021-08-03 22:51 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Parallel submission aka multi-bb execbuf (rev2) Patchwork
2021-08-03 22:53 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-08-03 22:57 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
2021-08-03 23:19 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-08-05 3:53 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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