From: John.C.Harrison@Intel.com
To: Intel-GFX@Lists.FreeDesktop.Org
Cc: DRI-Devel@Lists.FreeDesktop.Org,
John Harrison <John.C.Harrison@Intel.com>,
Matthew Brost <matthew.brost@intel.com>
Subject: [Intel-gfx] [PATCH 0/8] [CI] Enable GuC submission by default on DG1
Date: Tue, 7 Sep 2021 18:42:51 -0700 [thread overview]
Message-ID: <20210908014259.50346-1-John.C.Harrison@Intel.com> (raw)
From: John Harrison <John.C.Harrison@Intel.com>
Minimum set of patches to enable GuC submission on DG1 and enable it by
default.
A little difficult to test as IGTs do not work with DG1 due to a bunch
of uAPI features being disabled (e.g. relocations, caching memory
options, etc...). Hence extra patches at the end to enable some
features / add debugging info.
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Daniele Ceraolo Spurio (1):
drm/i915/guc: put all guc objects in lmem when available
Matthew Brost (5):
drm/i915/guc: Add DG1 GuC / HuC firmware defs
drm/i915/guc: Enable GuC submission by default on DG1
Me: Allow relocs on DG1 for CI
Me: Workaround LMEM blow up
Me: Dump GuC log to dmesg on SLPC load failure
Venkata Sandeep Dhanalakota (1):
drm/i915: Do not define vma on stack
Vinay Belgaumkar (1):
drm/i915: Get PM ref before accessing HW register
.../gpu/drm/i915/gem/i915_gem_execbuffer.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_lmem.c | 26 +++++
drivers/gpu/drm/i915/gem/i915_gem_lmem.h | 4 +
drivers/gpu/drm/i915/gt/intel_rps.c | 8 +-
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 9 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 13 ++-
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 3 +
drivers/gpu/drm/i915/gt/uc/intel_huc.c | 14 ++-
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 90 ++++++++++++++---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h | 2 +
drivers/gpu/drm/i915/i915_gpu_error.c | 99 ++++++++++++++++++-
drivers/gpu/drm/i915/i915_gpu_error.h | 3 +
13 files changed, 251 insertions(+), 24 deletions(-)
--
2.25.1
next reply other threads:[~2021-09-08 1:43 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-08 1:42 John.C.Harrison [this message]
2021-09-08 1:42 ` [Intel-gfx] [PATCH 1/8] drm/i915: Do not define vma on stack John.C.Harrison
2021-09-08 1:42 ` [Intel-gfx] [PATCH 2/8] drm/i915/guc: put all guc objects in lmem when available John.C.Harrison
2021-09-08 1:42 ` [Intel-gfx] [PATCH 3/8] drm/i915/guc: Add DG1 GuC / HuC firmware defs John.C.Harrison
2021-09-08 1:42 ` [Intel-gfx] [PATCH 4/8] drm/i915/guc: Enable GuC submission by default on DG1 John.C.Harrison
2021-09-08 1:42 ` [Intel-gfx] [PATCH 5/8] Me: Allow relocs on DG1 for CI John.C.Harrison
2021-09-08 1:42 ` [Intel-gfx] [PATCH 6/8] Me: Workaround LMEM blow up John.C.Harrison
2021-09-08 1:42 ` [Intel-gfx] [PATCH 7/8] Me: Dump GuC log to dmesg on SLPC load failure John.C.Harrison
2021-09-08 1:42 ` [Intel-gfx] [PATCH 8/8] drm/i915: Get PM ref before accessing HW register John.C.Harrison
2021-09-08 1:53 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Enable GuC submission by default on DG1 (rev3) Patchwork
2021-09-08 1:55 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-09-08 2:28 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-09-08 7:58 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-09-09 16:23 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Enable GuC submission by default on DG1 (rev4) Patchwork
2021-09-09 16:24 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-09-09 16:52 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-09-09 18:27 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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