From: John.C.Harrison@Intel.com
To: Intel-GFX@Lists.FreeDesktop.Org
Cc: DRI-Devel@Lists.FreeDesktop.Org, Matthew Brost <matthew.brost@intel.com>
Subject: [Intel-gfx] [PATCH 3/8] drm/i915/guc: Add DG1 GuC / HuC firmware defs
Date: Tue, 7 Sep 2021 18:42:54 -0700 [thread overview]
Message-ID: <20210908014259.50346-4-John.C.Harrison@Intel.com> (raw)
In-Reply-To: <20210908014259.50346-1-John.C.Harrison@Intel.com>
From: Matthew Brost <matthew.brost@intel.com>
Add DG1 GuC / HuC firmware defs
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index f8cb00ffb506..a685d563df72 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -51,6 +51,7 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw,
#define INTEL_UC_FIRMWARE_DEFS(fw_def, guc_def, huc_def) \
fw_def(ALDERLAKE_P, 0, guc_def(adlp, 62, 0, 3), huc_def(tgl, 7, 9, 3)) \
fw_def(ALDERLAKE_S, 0, guc_def(tgl, 62, 0, 0), huc_def(tgl, 7, 9, 3)) \
+ fw_def(DG1, 0, guc_def(dg1, 62, 0, 0), huc_def(dg1, 7, 9, 3)) \
fw_def(ROCKETLAKE, 0, guc_def(tgl, 62, 0, 0), huc_def(tgl, 7, 9, 3)) \
fw_def(TIGERLAKE, 0, guc_def(tgl, 62, 0, 0), huc_def(tgl, 7, 9, 3)) \
fw_def(JASPERLAKE, 0, guc_def(ehl, 62, 0, 0), huc_def(ehl, 9, 0, 0)) \
--
2.25.1
next prev parent reply other threads:[~2021-09-08 1:43 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-08 1:42 [Intel-gfx] [PATCH 0/8] [CI] Enable GuC submission by default on DG1 John.C.Harrison
2021-09-08 1:42 ` [Intel-gfx] [PATCH 1/8] drm/i915: Do not define vma on stack John.C.Harrison
2021-09-08 1:42 ` [Intel-gfx] [PATCH 2/8] drm/i915/guc: put all guc objects in lmem when available John.C.Harrison
2021-09-08 1:42 ` John.C.Harrison [this message]
2021-09-08 1:42 ` [Intel-gfx] [PATCH 4/8] drm/i915/guc: Enable GuC submission by default on DG1 John.C.Harrison
2021-09-08 1:42 ` [Intel-gfx] [PATCH 5/8] Me: Allow relocs on DG1 for CI John.C.Harrison
2021-09-08 1:42 ` [Intel-gfx] [PATCH 6/8] Me: Workaround LMEM blow up John.C.Harrison
2021-09-08 1:42 ` [Intel-gfx] [PATCH 7/8] Me: Dump GuC log to dmesg on SLPC load failure John.C.Harrison
2021-09-08 1:42 ` [Intel-gfx] [PATCH 8/8] drm/i915: Get PM ref before accessing HW register John.C.Harrison
2021-09-08 1:53 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Enable GuC submission by default on DG1 (rev3) Patchwork
2021-09-08 1:55 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-09-08 2:28 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-09-08 7:58 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-09-09 16:23 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Enable GuC submission by default on DG1 (rev4) Patchwork
2021-09-09 16:24 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-09-09 16:52 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-09-09 18:27 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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