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From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: stable@vger.kernel.org
Subject: [Intel-gfx] [PATCH v2 1/6] drm/i915: Correctly populate use_sagv_wm for all pipes
Date: Wed, 16 Feb 2022 19:42:45 +0200	[thread overview]
Message-ID: <20220216174250.4449-2-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20220216174250.4449-1-ville.syrjala@linux.intel.com>

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

When changing between SAGV vs. no SAGV on tgl+ we have to
update the use_sagv_wm flag for all the crtcs or else
an active pipe not already in the state will end up using
the wrong watermarks. That is especially bad when we end up
with the tighter non-SAGV watermarks with SAGV enabled.
Usually ends up in underruns.

Cc: stable@vger.kernel.org
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Fixes: 7241c57d3140 ("drm/i915: Add TGL+ SAGV support")
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 22 +++++++++++-----------
 1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9f5e3c399f8d..bd32fd70e6b2 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4007,6 +4007,17 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
 			return ret;
 	}
 
+	if (intel_can_enable_sagv(dev_priv, new_bw_state) !=
+	    intel_can_enable_sagv(dev_priv, old_bw_state)) {
+		ret = intel_atomic_serialize_global_state(&new_bw_state->base);
+		if (ret)
+			return ret;
+	} else if (new_bw_state->pipe_sagv_reject != old_bw_state->pipe_sagv_reject) {
+		ret = intel_atomic_lock_global_state(&new_bw_state->base);
+		if (ret)
+			return ret;
+	}
+
 	for_each_new_intel_crtc_in_state(state, crtc,
 					 new_crtc_state, i) {
 		struct skl_pipe_wm *pipe_wm = &new_crtc_state->wm.skl.optimal;
@@ -4022,17 +4033,6 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
 			intel_can_enable_sagv(dev_priv, new_bw_state);
 	}
 
-	if (intel_can_enable_sagv(dev_priv, new_bw_state) !=
-	    intel_can_enable_sagv(dev_priv, old_bw_state)) {
-		ret = intel_atomic_serialize_global_state(&new_bw_state->base);
-		if (ret)
-			return ret;
-	} else if (new_bw_state->pipe_sagv_reject != old_bw_state->pipe_sagv_reject) {
-		ret = intel_atomic_lock_global_state(&new_bw_state->base);
-		if (ret)
-			return ret;
-	}
-
 	return 0;
 }
 
-- 
2.34.1


  reply	other threads:[~2022-02-16 17:43 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-02-16 17:42 [Intel-gfx] [PATCH v2 0/6] drm/i915: SAGV fixes Ville Syrjala
2022-02-16 17:42 ` Ville Syrjala [this message]
2022-02-16 17:42 ` [Intel-gfx] [PATCH v2 2/6] drm/i915: Fix bw atomic check when switching between SAGV vs. no SAGV Ville Syrjala
2022-02-17 18:29   ` Lisovskiy, Stanislav
2022-02-16 17:42 ` [Intel-gfx] [PATCH v2 3/6] drm/i915: Split pre-icl vs. icl+ SAGV hooks apart Ville Syrjala
2022-02-16 17:42 ` [Intel-gfx] [PATCH v2 4/6] drm/i915: Pimp icl+ sagv pre/post update Ville Syrjala
2022-02-16 17:42 ` [Intel-gfx] [PATCH v2 5/6] drm/i915: Extract icl_qgv_points_mask() Ville Syrjala
2022-02-16 17:42 ` [Intel-gfx] [PATCH v2 6/6] drm/i915: Extract intel_bw_check_data_rate() Ville Syrjala
2022-02-17 18:33   ` Lisovskiy, Stanislav
2022-02-17 11:08 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: SAGV fixes (rev2) Patchwork
2022-02-17 20:03 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2022-02-18  4:41   ` Ville Syrjälä

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