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From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v2 4/6] drm/i915: Pimp icl+ sagv pre/post update
Date: Wed, 16 Feb 2022 19:42:48 +0200	[thread overview]
Message-ID: <20220216174250.4449-5-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20220216174250.4449-1-ville.syrjala@linux.intel.com>

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Add some debugs on what exactly we're doing to the QGV point mask
in the icl+ sagv pre/post plane update hooks. Currently we're just
guessing.

v2: s/u32/u16/ for consistency with the mask sizes (Stan)

Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 37 ++++++++++++++++-----------------
 1 file changed, 18 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9e2c339f8d16..f4324c0326cd 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3814,26 +3814,22 @@ static void icl_sagv_pre_plane_update(struct intel_atomic_state *state)
 		intel_atomic_get_old_bw_state(state);
 	const struct intel_bw_state *new_bw_state =
 		intel_atomic_get_new_bw_state(state);
-	u32 new_mask;
+	u16 old_mask, new_mask;
 
 	if (!new_bw_state)
 		return;
 
-	/*
-	 * Nothing to mask
-	 */
-	if (new_bw_state->qgv_points_mask == old_bw_state->qgv_points_mask)
-		return;
-
+	old_mask = old_bw_state->qgv_points_mask;
 	new_mask = old_bw_state->qgv_points_mask | new_bw_state->qgv_points_mask;
 
-	/*
-	 * If new mask is zero - means there is nothing to mask,
-	 * we can only unmask, which should be done in unmask.
-	 */
-	if (!new_mask)
+	if (old_mask == new_mask)
 		return;
 
+	WARN_ON(!new_bw_state->base.changed);
+
+	drm_dbg_kms(&dev_priv->drm, "Restricting QGV points: 0x%x -> 0x%x\n",
+		    old_mask, new_mask);
+
 	/*
 	 * Restrict required qgv points before updating the configuration.
 	 * According to BSpec we can't mask and unmask qgv points at the same
@@ -3850,19 +3846,22 @@ static void icl_sagv_post_plane_update(struct intel_atomic_state *state)
 		intel_atomic_get_old_bw_state(state);
 	const struct intel_bw_state *new_bw_state =
 		intel_atomic_get_new_bw_state(state);
-	u32 new_mask = 0;
+	u16 old_mask, new_mask;
 
 	if (!new_bw_state)
 		return;
 
-	/*
-	 * Nothing to unmask
-	 */
-	if (new_bw_state->qgv_points_mask == old_bw_state->qgv_points_mask)
-		return;
-
+	old_mask = old_bw_state->qgv_points_mask | new_bw_state->qgv_points_mask;
 	new_mask = new_bw_state->qgv_points_mask;
 
+	if (old_mask == new_mask)
+		return;
+
+	WARN_ON(!new_bw_state->base.changed);
+
+	drm_dbg_kms(&dev_priv->drm, "Relaxing QGV points: 0x%x -> 0x%x\n",
+		    old_mask, new_mask);
+
 	/*
 	 * Allow required qgv points after updating the configuration.
 	 * According to BSpec we can't mask and unmask qgv points at the same
-- 
2.34.1


  parent reply	other threads:[~2022-02-16 17:43 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-02-16 17:42 [Intel-gfx] [PATCH v2 0/6] drm/i915: SAGV fixes Ville Syrjala
2022-02-16 17:42 ` [Intel-gfx] [PATCH v2 1/6] drm/i915: Correctly populate use_sagv_wm for all pipes Ville Syrjala
2022-02-16 17:42 ` [Intel-gfx] [PATCH v2 2/6] drm/i915: Fix bw atomic check when switching between SAGV vs. no SAGV Ville Syrjala
2022-02-17 18:29   ` Lisovskiy, Stanislav
2022-02-16 17:42 ` [Intel-gfx] [PATCH v2 3/6] drm/i915: Split pre-icl vs. icl+ SAGV hooks apart Ville Syrjala
2022-02-16 17:42 ` Ville Syrjala [this message]
2022-02-16 17:42 ` [Intel-gfx] [PATCH v2 5/6] drm/i915: Extract icl_qgv_points_mask() Ville Syrjala
2022-02-16 17:42 ` [Intel-gfx] [PATCH v2 6/6] drm/i915: Extract intel_bw_check_data_rate() Ville Syrjala
2022-02-17 18:33   ` Lisovskiy, Stanislav
2022-02-17 11:08 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: SAGV fixes (rev2) Patchwork
2022-02-17 20:03 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2022-02-18  4:41   ` Ville Syrjälä

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