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From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v2 5/6] drm/i915: Extract icl_qgv_points_mask()
Date: Wed, 16 Feb 2022 19:42:49 +0200	[thread overview]
Message-ID: <20220216174250.4449-6-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20220216174250.4449-1-ville.syrjala@linux.intel.com>

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Declutter intel_bw_atomic_check() a bit by pulling
the max QGV mask calculation out.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_bw.c | 35 ++++++++++++++++---------
 1 file changed, 22 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index d72ccee7d53b..fa03f0935b6d 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -815,6 +815,26 @@ int intel_bw_calc_min_cdclk(struct intel_atomic_state *state)
 	return 0;
 }
 
+static u16 icl_qgv_points_mask(struct drm_i915_private *i915)
+{
+	unsigned int num_psf_gv_points = i915->max_bw[0].num_psf_gv_points;
+	unsigned int num_qgv_points = i915->max_bw[0].num_qgv_points;
+	u16 mask = 0;
+
+	/*
+	 * We can _not_ use the whole ADLS_QGV_PT_MASK here, as PCode rejects
+	 * it with failure if we try masking any unadvertised points.
+	 * So need to operate only with those returned from PCode.
+	 */
+	if (num_qgv_points > 0)
+		mask |= REG_GENMASK(num_qgv_points - 1, 0);
+
+	if (num_psf_gv_points > 0)
+		mask |= REG_GENMASK(num_psf_gv_points - 1, 0) << ADLS_PSF_PT_SHIFT;
+
+	return mask;
+}
+
 int intel_bw_atomic_check(struct intel_atomic_state *state)
 {
 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
@@ -829,23 +849,11 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
 	unsigned int max_bw_point = 0, max_bw = 0;
 	unsigned int num_qgv_points = dev_priv->max_bw[0].num_qgv_points;
 	unsigned int num_psf_gv_points = dev_priv->max_bw[0].num_psf_gv_points;
-	u32 mask = 0;
 
 	/* FIXME earlier gens need some checks too */
 	if (DISPLAY_VER(dev_priv) < 11)
 		return 0;
 
-	/*
-	 * We can _not_ use the whole ADLS_QGV_PT_MASK here, as PCode rejects
-	 * it with failure if we try masking any unadvertised points.
-	 * So need to operate only with those returned from PCode.
-	 */
-	if (num_qgv_points > 0)
-		mask |= REG_GENMASK(num_qgv_points - 1, 0);
-
-	if (num_psf_gv_points > 0)
-		mask |= REG_GENMASK(num_psf_gv_points - 1, 0) << ADLS_PSF_PT_SHIFT;
-
 	/*
 	 * If we already have the bw state then recompute everything
 	 * even if pipe data_rate / active_planes didn't change.
@@ -970,7 +978,8 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
 	 * We store the ones which need to be masked as that is what PCode
 	 * actually accepts as a parameter.
 	 */
-	new_bw_state->qgv_points_mask = ~allowed_points & mask;
+	new_bw_state->qgv_points_mask = ~allowed_points &
+		icl_qgv_points_mask(dev_priv);
 
 	old_bw_state = intel_atomic_get_old_bw_state(state);
 	/*
-- 
2.34.1


  parent reply	other threads:[~2022-02-16 17:43 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-02-16 17:42 [Intel-gfx] [PATCH v2 0/6] drm/i915: SAGV fixes Ville Syrjala
2022-02-16 17:42 ` [Intel-gfx] [PATCH v2 1/6] drm/i915: Correctly populate use_sagv_wm for all pipes Ville Syrjala
2022-02-16 17:42 ` [Intel-gfx] [PATCH v2 2/6] drm/i915: Fix bw atomic check when switching between SAGV vs. no SAGV Ville Syrjala
2022-02-17 18:29   ` Lisovskiy, Stanislav
2022-02-16 17:42 ` [Intel-gfx] [PATCH v2 3/6] drm/i915: Split pre-icl vs. icl+ SAGV hooks apart Ville Syrjala
2022-02-16 17:42 ` [Intel-gfx] [PATCH v2 4/6] drm/i915: Pimp icl+ sagv pre/post update Ville Syrjala
2022-02-16 17:42 ` Ville Syrjala [this message]
2022-02-16 17:42 ` [Intel-gfx] [PATCH v2 6/6] drm/i915: Extract intel_bw_check_data_rate() Ville Syrjala
2022-02-17 18:33   ` Lisovskiy, Stanislav
2022-02-17 11:08 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: SAGV fixes (rev2) Patchwork
2022-02-17 20:03 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2022-02-18  4:41   ` Ville Syrjälä

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