public inbox for intel-gfx@lists.freedesktop.org
 help / color / mirror / Atom feed
From: Ramalingam C <ramalingam.c@intel.com>
To: intel-gfx <intel-gfx@lists.freedesktop.org>,
	dri-devel <dri-devel@lists.freedesktop.org>
Cc: "Thomas Hellström" <thomas.hellstrom@linux.intel.com>,
	"Simon Ser" <contact@emersion.fr>,
	lucas.demarchi@intel.com,
	"Kenneth Graunke" <kenneth@whitecape.org>,
	"Slawomir Milczarek" <slawomir.milczarek@intel.com>,
	"Pekka Paalanen" <ppaalanen@gmail.com>,
	"Matthew Auld" <matthew.auld@intel.com>,
	mesa-dev@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 12/15] drm/i915/uapi: document behaviour for DG2 64K support
Date: Sat, 19 Feb 2022 00:17:49 +0530	[thread overview]
Message-ID: <20220218184752.7524-13-ramalingam.c@intel.com> (raw)
In-Reply-To: <20220218184752.7524-1-ramalingam.c@intel.com>

From: Matthew Auld <matthew.auld@intel.com>

On discrete platforms like DG2, we need to support a minimum page size
of 64K when dealing with device local-memory. This is quite tricky for
various reasons, so try to document the new implicit uapi for this.

v4: Kdoc modification.
v3: fix typos and less emphasis
v2: Fixed suggestions on formatting [Daniel]

Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
Acked-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Ramalingam C <ramalingam.c@intel.com>
Reviewed-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
cc: Simon Ser <contact@emersion.fr>
cc: Pekka Paalanen <ppaalanen@gmail.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Cc: mesa-dev@lists.freedesktop.org
Cc: Tony Ye <tony.ye@intel.com>
Cc: Slawomir Milczarek <slawomir.milczarek@intel.com>
---
 include/uapi/drm/i915_drm.h | 45 ++++++++++++++++++++++++++++++++-----
 1 file changed, 40 insertions(+), 5 deletions(-)

diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 914ebd9290e5..05c3642aaece 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -1118,10 +1118,16 @@ struct drm_i915_gem_exec_object2 {
 	/**
 	 * When the EXEC_OBJECT_PINNED flag is specified this is populated by
 	 * the user with the GTT offset at which this object will be pinned.
+	 *
 	 * When the I915_EXEC_NO_RELOC flag is specified this must contain the
 	 * presumed_offset of the object.
+	 *
 	 * During execbuffer2 the kernel populates it with the value of the
 	 * current GTT offset of the object, for future presumed_offset writes.
+	 *
+	 * See struct drm_i915_gem_create_ext for the rules when dealing with
+	 * alignment restrictions with I915_MEMORY_CLASS_DEVICE, on devices with
+	 * minimum page sizes, like DG2.
 	 */
 	__u64 offset;
 
@@ -3144,11 +3150,40 @@ struct drm_i915_gem_create_ext {
 	 *
 	 * The (page-aligned) allocated size for the object will be returned.
 	 *
-	 * Note that for some devices we have might have further minimum
-	 * page-size restrictions(larger than 4K), like for device local-memory.
-	 * However in general the final size here should always reflect any
-	 * rounding up, if for example using the I915_GEM_CREATE_EXT_MEMORY_REGIONS
-	 * extension to place the object in device local-memory.
+	 *
+	 * DG2 64K min page size implications:
+	 *
+	 * On discrete platforms, starting from DG2, we have to contend with GTT
+	 * page size restrictions when dealing with I915_MEMORY_CLASS_DEVICE
+	 * objects.  Specifically the hardware only supports 64K or larger GTT
+	 * page sizes for such memory. The kernel will already ensure that all
+	 * I915_MEMORY_CLASS_DEVICE memory is allocated using 64K or larger page
+	 * sizes underneath.
+	 *
+	 * Note that the returned size here will always reflect any required
+	 * rounding up done by the kernel, i.e 4K will now become 64K on devices
+	 * such as DG2.
+	 *
+	 * Special DG2 GTT address alignment requirement:
+	 *
+	 * The GTT alignment will also need to be at least 2M for such objects.
+	 *
+	 * Note that due to how the hardware implements 64K GTT page support, we
+	 * have some further complications:
+	 *
+	 *   1) The entire PDE (which covers a 2MB virtual address range), must
+	 *   contain only 64K PTEs, i.e mixing 4K and 64K PTEs in the same
+	 *   PDE is forbidden by the hardware.
+	 *
+	 *   2) We still need to support 4K PTEs for I915_MEMORY_CLASS_SYSTEM
+	 *   objects.
+	 *
+	 * To keep things simple for userland, we mandate that any GTT mappings
+	 * must be aligned to and rounded up to 2MB. The kernel will internally
+	 * pad them out to the next 2MB boundary. As this only wastes virtual
+	 * address space and avoids userland having to copy any needlessly
+	 * complicated PDE sharing scheme (coloring) and only affects DG2, this
+	 * is deemed to be a good compromise.
 	 */
 	__u64 size;
 	/**
-- 
2.20.1


  parent reply	other threads:[~2022-02-18 18:48 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-02-18 18:47 [Intel-gfx] [PATCH 00/15] drm/i915: Enable DG2 Ramalingam C
2022-02-18 18:47 ` [Intel-gfx] [PATCH 01/15] drm/i915/dg2: Define GuC firmware version for DG2 Ramalingam C
2022-02-18 19:14   ` Ceraolo Spurio, Daniele
2022-02-18 18:47 ` [Intel-gfx] [PATCH 02/15] drm/i915: Fix for PHY_MISC_TC1 offset Ramalingam C
2022-02-18 18:47 ` [Intel-gfx] [PATCH 03/15] drm/i915/dg2: Drop 38.4 MHz MPLLB tables Ramalingam C
2022-02-18 18:47 ` [Intel-gfx] [PATCH 04/15] drm/i915/dg2: Enable 5th port Ramalingam C
2022-02-18 18:47 ` [Intel-gfx] [PATCH 05/15] drm/i915: add needs_compact_pt flag Ramalingam C
2022-02-18 18:47 ` [Intel-gfx] [PATCH 06/15] drm/i915: enforce min GTT alignment for discrete cards Ramalingam C
2022-03-03  9:43   ` Jani Nikula
2022-02-18 18:47 ` [Intel-gfx] [PATCH 07/15] drm/i915: support 64K GTT pages " Ramalingam C
2022-02-18 18:47 ` [Intel-gfx] [PATCH 08/15] drm/i915: add gtt misalignment test Ramalingam C
2022-02-18 18:47 ` [Intel-gfx] [PATCH 09/15] drm/i915/gtt: allow overriding the pt alignment Ramalingam C
2022-02-18 18:47 ` [Intel-gfx] [PATCH 10/15] drm/i915/gtt: add xehpsdv_ppgtt_insert_entry Ramalingam C
2022-02-18 18:47 ` [Intel-gfx] [PATCH 11/15] drm/i915/migrate: add acceleration support for DG2 Ramalingam C
2022-02-18 18:47 ` Ramalingam C [this message]
2022-02-18 18:47 ` [Intel-gfx] [PATCH 13/15] drm/i915/xehpsdv: Add has_flat_ccs to device info Ramalingam C
2022-02-18 18:47 ` [Intel-gfx] [PATCH 14/15] drm/i915/lmem: Enable lmem for platforms with Flat CCS Ramalingam C
2022-02-18 18:47 ` [Intel-gfx] [PATCH 15/15] drm/i915/gt: Clear compress metadata for Xe_HP platforms Ramalingam C
2022-02-19  1:47   ` Matt Roper
2022-02-27 16:52     ` Ramalingam C
2022-03-03  5:28       ` Matt Roper
2022-02-18 19:09 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Enable DG2 Patchwork
2022-02-18 19:10 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-02-18 19:38 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-02-19 11:53 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2022-02-20 10:18 ` [Intel-gfx] [PATCH 00/15] " Lucas De Marchi

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20220218184752.7524-13-ramalingam.c@intel.com \
    --to=ramalingam.c@intel.com \
    --cc=contact@emersion.fr \
    --cc=dri-devel@lists.freedesktop.org \
    --cc=intel-gfx@lists.freedesktop.org \
    --cc=kenneth@whitecape.org \
    --cc=lucas.demarchi@intel.com \
    --cc=matthew.auld@intel.com \
    --cc=mesa-dev@lists.freedesktop.org \
    --cc=ppaalanen@gmail.com \
    --cc=slawomir.milczarek@intel.com \
    --cc=thomas.hellstrom@linux.intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox