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From: Ramalingam C <ramalingam.c@intel.com>
To: intel-gfx <intel-gfx@lists.freedesktop.org>,
	dri-devel <dri-devel@lists.freedesktop.org>
Cc: lucas.demarchi@intel.com, CQ Tang <cq.tang@intel.com>,
	Matthew Auld <matthew.auld@intel.com>
Subject: [Intel-gfx] [PATCH 13/15] drm/i915/xehpsdv: Add has_flat_ccs to device info
Date: Sat, 19 Feb 2022 00:17:50 +0530	[thread overview]
Message-ID: <20220218184752.7524-14-ramalingam.c@intel.com> (raw)
In-Reply-To: <20220218184752.7524-1-ramalingam.c@intel.com>

From: CQ Tang <cq.tang@intel.com>

Platforms of XeHP and beyond support 3D surface (buffer) compression and
various compression formats. This is accomplished by an additional
compression control state (CCS) stored for each surface.

Gen 12 devices(TGL family and DG1) stores compression states in a separate
region of memory. It is managed by user-space and has an associated set of
user-space managed page tables used by hardware for address translation.

In Xe HP and beyond (XEHPSDV, DG2, etc), there is a new feature introduced
i.e Flat CCS. It replaced AUX page tables with a flat indexed region of
device memory for storing compression states.

Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Matthew Auld <matthew.auld@intel.com>
Signed-off-by: CQ Tang <cq.tang@intel.com>
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h          | 6 ++++++
 drivers/gpu/drm/i915/i915_pci.c          | 1 +
 drivers/gpu/drm/i915/intel_device_info.h | 1 +
 3 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4a3ac66e777a..1c2f4ae4ebf9 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1356,6 +1356,12 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i))
 #define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM)
 
+/*
+ * Platform has the dedicated compression control state for each lmem surfaces
+ * stored in lmem to support the 3D and media compression formats.
+ */
+#define HAS_FLAT_CCS(dev_priv)   (INTEL_INFO(dev_priv)->has_flat_ccs)
+
 #define HAS_GT_UC(dev_priv)	(INTEL_INFO(dev_priv)->has_gt_uc)
 
 #define HAS_POOLED_EU(dev_priv)	(INTEL_INFO(dev_priv)->has_pooled_eu)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 8df8887d76ae..f449c454b6f8 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1005,6 +1005,7 @@ static const struct intel_device_info adl_p_info = {
 	XE_HP_PAGE_SIZES, \
 	.dma_mask_size = 46, \
 	.has_64bit_reloc = 1, \
+	.has_flat_ccs = 1, \
 	.has_global_mocs = 1, \
 	.has_gt_uc = 1, \
 	.has_llc = 1, \
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index f75673da768d..2508a47fb3f5 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -134,6 +134,7 @@ enum intel_ppgtt_type {
 	func(needs_compact_pt); \
 	func(gpu_reset_clobbers_display); \
 	func(has_reset_engine); \
+	func(has_flat_ccs); \
 	func(has_global_mocs); \
 	func(has_gt_uc); \
 	func(has_guc_deprivilege); \
-- 
2.20.1


  parent reply	other threads:[~2022-02-18 18:48 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-02-18 18:47 [Intel-gfx] [PATCH 00/15] drm/i915: Enable DG2 Ramalingam C
2022-02-18 18:47 ` [Intel-gfx] [PATCH 01/15] drm/i915/dg2: Define GuC firmware version for DG2 Ramalingam C
2022-02-18 19:14   ` Ceraolo Spurio, Daniele
2022-02-18 18:47 ` [Intel-gfx] [PATCH 02/15] drm/i915: Fix for PHY_MISC_TC1 offset Ramalingam C
2022-02-18 18:47 ` [Intel-gfx] [PATCH 03/15] drm/i915/dg2: Drop 38.4 MHz MPLLB tables Ramalingam C
2022-02-18 18:47 ` [Intel-gfx] [PATCH 04/15] drm/i915/dg2: Enable 5th port Ramalingam C
2022-02-18 18:47 ` [Intel-gfx] [PATCH 05/15] drm/i915: add needs_compact_pt flag Ramalingam C
2022-02-18 18:47 ` [Intel-gfx] [PATCH 06/15] drm/i915: enforce min GTT alignment for discrete cards Ramalingam C
2022-03-03  9:43   ` Jani Nikula
2022-02-18 18:47 ` [Intel-gfx] [PATCH 07/15] drm/i915: support 64K GTT pages " Ramalingam C
2022-02-18 18:47 ` [Intel-gfx] [PATCH 08/15] drm/i915: add gtt misalignment test Ramalingam C
2022-02-18 18:47 ` [Intel-gfx] [PATCH 09/15] drm/i915/gtt: allow overriding the pt alignment Ramalingam C
2022-02-18 18:47 ` [Intel-gfx] [PATCH 10/15] drm/i915/gtt: add xehpsdv_ppgtt_insert_entry Ramalingam C
2022-02-18 18:47 ` [Intel-gfx] [PATCH 11/15] drm/i915/migrate: add acceleration support for DG2 Ramalingam C
2022-02-18 18:47 ` [Intel-gfx] [PATCH 12/15] drm/i915/uapi: document behaviour for DG2 64K support Ramalingam C
2022-02-18 18:47 ` Ramalingam C [this message]
2022-02-18 18:47 ` [Intel-gfx] [PATCH 14/15] drm/i915/lmem: Enable lmem for platforms with Flat CCS Ramalingam C
2022-02-18 18:47 ` [Intel-gfx] [PATCH 15/15] drm/i915/gt: Clear compress metadata for Xe_HP platforms Ramalingam C
2022-02-19  1:47   ` Matt Roper
2022-02-27 16:52     ` Ramalingam C
2022-03-03  5:28       ` Matt Roper
2022-02-18 19:09 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Enable DG2 Patchwork
2022-02-18 19:10 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-02-18 19:38 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-02-19 11:53 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2022-02-20 10:18 ` [Intel-gfx] [PATCH 00/15] " Lucas De Marchi

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