From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v2 0/9] drm/i915: Fix bandwith related cdclk calculations
Date: Thu, 3 Mar 2022 21:11:58 +0200 [thread overview]
Message-ID: <20220303191207.27931-1-ville.syrjala@linux.intel.com> (raw)
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Fix up the dbuf bandwidth cdclk calculations to match the spec,
and also implement the cdclk based pipe max bandwidth limit.
TODO: intel_bw contains two orthogonal things (qgv vs. cdclk).
We should probably just split it into two parts to life
less confusing. But as usual naming is hard so I didn't
go for that yet...
v2: Rebased due to the async flip wm0/ddb stuff
Ville Syrjälä (9):
drm/i915: Tweak plane ddb allocation tracking
drm/i915: Split plane data_rate into data_rate+data_rate_y
drm/i915: Pre-calculate plane relative data rate
drm/i915: Remove total[] and uv_total[] from ddb allocation
drm/i915: Nuke intel_bw_calc_min_cdclk()
drm/i915: Round up when calculating display bandwidth requirements
drm/i915: Properly write lock bw_state when it changes
drm/i915: Fix DBUF bandwidth vs. cdclk handling
drm/i915: Add "maximum pipe read bandwidth" checks
.../gpu/drm/i915/display/intel_atomic_plane.c | 120 ++++--
.../gpu/drm/i915/display/intel_atomic_plane.h | 3 +-
drivers/gpu/drm/i915/display/intel_bw.c | 254 ++++++++-----
drivers/gpu/drm/i915/display/intel_bw.h | 12 +-
drivers/gpu/drm/i915/display/intel_cdclk.c | 96 ++---
drivers/gpu/drm/i915/display/intel_cdclk.h | 2 +
drivers/gpu/drm/i915/display/intel_display.c | 17 +-
.../drm/i915/display/intel_display_debugfs.c | 4 +-
.../drm/i915/display/intel_display_types.h | 16 +-
drivers/gpu/drm/i915/intel_pm.c | 359 ++++++------------
10 files changed, 431 insertions(+), 452 deletions(-)
--
2.34.1
next reply other threads:[~2022-03-03 19:12 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-03 19:11 Ville Syrjala [this message]
2022-03-03 19:11 ` [Intel-gfx] [PATCH v2 1/9] drm/i915: Tweak plane ddb allocation tracking Ville Syrjala
2022-03-03 19:12 ` [Intel-gfx] [PATCH v2 2/9] drm/i915: Split plane data_rate into data_rate+data_rate_y Ville Syrjala
2022-03-03 19:12 ` [Intel-gfx] [PATCH v2 3/9] drm/i915: Pre-calculate plane relative data rate Ville Syrjala
2022-03-03 19:12 ` [Intel-gfx] [PATCH v2 4/9] drm/i915: Remove total[] and uv_total[] from ddb allocation Ville Syrjala
2022-03-03 19:12 ` [Intel-gfx] [PATCH v2 5/9] drm/i915: Nuke intel_bw_calc_min_cdclk() Ville Syrjala
2022-03-03 19:12 ` [Intel-gfx] [PATCH v2 6/9] drm/i915: Round up when calculating display bandwidth requirements Ville Syrjala
2022-03-10 7:46 ` Lisovskiy, Stanislav
2022-03-03 19:12 ` [Intel-gfx] [PATCH v2 7/9] drm/i915: Properly write lock bw_state when it changes Ville Syrjala
2022-03-10 7:47 ` Lisovskiy, Stanislav
2022-03-03 19:12 ` [Intel-gfx] [PATCH v2 8/9] drm/i915: Fix DBUF bandwidth vs. cdclk handling Ville Syrjala
2022-03-10 8:22 ` Lisovskiy, Stanislav
2022-03-10 8:59 ` Ville Syrjälä
2022-03-10 12:37 ` Lisovskiy, Stanislav
2022-03-03 19:12 ` [Intel-gfx] [PATCH v2 9/9] drm/i915: Add "maximum pipe read bandwidth" checks Ville Syrjala
2022-03-10 14:06 ` Lisovskiy, Stanislav
2022-03-03 20:00 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Fix bandwith related cdclk calculations (rev2) Patchwork
2022-03-03 20:01 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-03-03 20:29 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-03-04 9:14 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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