[Intel-gfx] [PATCH 0/2] Splitting intel-gtt calls for non-x86 platforms

[Intel-gfx] [PATCH 0/2] Splitting intel-gtt calls for non-x86 platforms

[Casey Bowman]

The intel-gtt module defines some functions used by i915, but they are
only supported by x86 platforms. In order to bring i915 to a more
arch-neutral state, we split out these functions and provide stubs in
the case of non-x86 builds.

There may be a better filename choice for the files used in splitting
the calls, it's very much open to discussion.

Casey Bowman (2):
  drm/i915: Require INTEL_GTT to depend on X86
  drm/i915/gt: Split intel-gtt functions by arch

 drivers/gpu/drm/i915/Kconfig                |   2 +-
 drivers/gpu/drm/i915/Makefile               |   2 +
 drivers/gpu/drm/i915/gt/intel_ggtt.c        |  97 +----------------
 drivers/gpu/drm/i915/gt/intel_gt.c          |   6 +-
 drivers/gpu/drm/i915/gt/intel_gtt.h         |  10 ++
 drivers/gpu/drm/i915/gt/intel_gtt_support.c | 113 ++++++++++++++++++++
 drivers/gpu/drm/i915/gt/intel_gtt_support.h |  39 +++++++
 7 files changed, 172 insertions(+), 97 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/gt/intel_gtt_support.c
 create mode 100644 drivers/gpu/drm/i915/gt/intel_gtt_support.h

-- 
2.25.1

[Intel-gfx] [PATCH 1/2] drm/i915: Require INTEL_GTT to depend on X86

[Casey Bowman]

The intel-gtt module is not used on other, non-x86 platforms, so we
will restrict it to x86 platforms only.

Signed-off-by: Casey Bowman <casey.g.bowman@intel.com>
---
 drivers/gpu/drm/i915/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig
index 63db8bcf03bf..b381e14863a6 100644
--- a/drivers/gpu/drm/i915/Kconfig
+++ b/drivers/gpu/drm/i915/Kconfig
@@ -4,7 +4,7 @@ config DRM_I915
 	depends on DRM
 	depends on X86 && PCI
 	depends on !PREEMPT_RT
-	select INTEL_GTT
+	select INTEL_GTT if X86
 	select INTERVAL_TREE
 	# we need shmfs for the swappable backing store, and in particular
 	# the shmem_readpage() which depends upon tmpfs
-- 
2.25.1

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Require INTEL_GTT to depend on X86

[Lucas De Marchi]

On Fri, Mar 18, 2022 at 07:00:41PM -0700, Casey Bowman wrote:
>The intel-gtt module is not used on other, non-x86 platforms, so we
>will restrict it to x86 platforms only.
>
>Signed-off-by: Casey Bowman <casey.g.bowman@intel.com>

this should probably be the second patch, not the first.



Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>


Lucas De Marchi


>---
> drivers/gpu/drm/i915/Kconfig | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
>diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig
>index 63db8bcf03bf..b381e14863a6 100644
>--- a/drivers/gpu/drm/i915/Kconfig
>+++ b/drivers/gpu/drm/i915/Kconfig
>@@ -4,7 +4,7 @@ config DRM_I915
> 	depends on DRM
> 	depends on X86 && PCI
> 	depends on !PREEMPT_RT
>-	select INTEL_GTT
>+	select INTEL_GTT if X86
> 	select INTERVAL_TREE
> 	# we need shmfs for the swappable backing store, and in particular
> 	# the shmem_readpage() which depends upon tmpfs
>-- 
>2.25.1
>

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Require INTEL_GTT to depend on X86

[Casey Bowman]

On 3/18/22 20:40, Lucas De Marchi wrote:
> On Fri, Mar 18, 2022 at 07:00:41PM -0700, Casey Bowman wrote:
>> The intel-gtt module is not used on other, non-x86 platforms, so we
>> will restrict it to x86 platforms only.
>>
>> Signed-off-by: Casey Bowman <casey.g.bowman@intel.com>
>
> this should probably be the second patch, not the first.

Good point, will rearrange in v2

Regards,
Casey

>
>
>
> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
>
>
> Lucas De Marchi
>
>
>> ---
>> drivers/gpu/drm/i915/Kconfig | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig
>> index 63db8bcf03bf..b381e14863a6 100644
>> --- a/drivers/gpu/drm/i915/Kconfig
>> +++ b/drivers/gpu/drm/i915/Kconfig
>> @@ -4,7 +4,7 @@ config DRM_I915
>>     depends on DRM
>>     depends on X86 && PCI
>>     depends on !PREEMPT_RT
>> -    select INTEL_GTT
>> +    select INTEL_GTT if X86
>>     select INTERVAL_TREE
>>     # we need shmfs for the swappable backing store, and in particular
>>     # the shmem_readpage() which depends upon tmpfs
>> -- 
>> 2.25.1
>>

[Intel-gfx] [PATCH 2/2] drm/i915/gt: Split intel-gtt functions by arch

[Casey Bowman]

Some functions defined in the intel-gtt module are used in several
areas, but is only supported on x86 platforms.

By separating these calls and their static underlying functions to
area, we are able to compile out these functions for non-x86 builds
and provide stubs for the non-x86 implementations.

Signed-off-by: Casey Bowman <casey.g.bowman@intel.com>
---
 drivers/gpu/drm/i915/Makefile               |   2 +
 drivers/gpu/drm/i915/gt/intel_ggtt.c        |  97 +----------------
 drivers/gpu/drm/i915/gt/intel_gt.c          |   6 +-
 drivers/gpu/drm/i915/gt/intel_gtt.h         |  10 ++
 drivers/gpu/drm/i915/gt/intel_gtt_support.c | 113 ++++++++++++++++++++
 drivers/gpu/drm/i915/gt/intel_gtt_support.h |  39 +++++++
 6 files changed, 171 insertions(+), 96 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/gt/intel_gtt_support.c
 create mode 100644 drivers/gpu/drm/i915/gt/intel_gtt_support.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 61b078bd1b32..cc332cb6833b 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -124,6 +124,8 @@ gt-y += \
 	gt/intel_workarounds.o \
 	gt/shmem_utils.o \
 	gt/sysfs_engines.o
+# x86 intel-gtt module support
+gt-$(CONFIG_X86) += gt/intel_gtt_support.o
 # autogenerated null render state
 gt-y += \
 	gt/gen6_renderstate.o \
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 04191fe2ee34..db2f1b12c273 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -3,14 +3,12 @@
  * Copyright © 2020 Intel Corporation
  */
 
-#include <linux/agp_backend.h>
 #include <linux/stop_machine.h>
 
 #include <asm/set_memory.h>
 #include <asm/smp.h>
 
 #include <drm/i915_drm.h>
-#include <drm/intel-gtt.h>
 
 #include "gem/i915_gem_lmem.h"
 
@@ -21,6 +19,7 @@
 #include "i915_vgpu.h"
 
 #include "intel_gtt.h"
+#include "intel_gtt_support.h"
 #include "gen8_ppgtt.h"
 
 static void i915_ggtt_color_adjust(const struct drm_mm_node *node,
@@ -98,7 +97,7 @@ int i915_ggtt_init_hw(struct drm_i915_private *i915)
  * Certain Gen5 chipsets require idling the GPU before
  * unmapping anything from the GTT when VT-d is enabled.
  */
-static bool needs_idle_maps(struct drm_i915_private *i915)
+bool needs_idle_maps(struct drm_i915_private *i915)
 {
 	/*
 	 * Query intel_iommu to see if we need the workaround. Presumably that
@@ -229,11 +228,6 @@ static void guc_ggtt_invalidate(struct i915_ggtt *ggtt)
 		intel_uncore_write_fw(uncore, GEN8_GTCR, GEN8_GTCR_INVALIDATE);
 }
 
-static void gmch_ggtt_invalidate(struct i915_ggtt *ggtt)
-{
-	intel_gtt_chipset_flush();
-}
-
 u64 gen8_ggtt_pte_encode(dma_addr_t addr,
 			 enum i915_cache_level level,
 			 u32 flags)
@@ -467,37 +461,7 @@ static void gen6_ggtt_clear_range(struct i915_address_space *vm,
 		iowrite32(scratch_pte, &gtt_base[i]);
 }
 
-static void i915_ggtt_insert_page(struct i915_address_space *vm,
-				  dma_addr_t addr,
-				  u64 offset,
-				  enum i915_cache_level cache_level,
-				  u32 unused)
-{
-	unsigned int flags = (cache_level == I915_CACHE_NONE) ?
-		AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
-
-	intel_gtt_insert_page(addr, offset >> PAGE_SHIFT, flags);
-}
-
-static void i915_ggtt_insert_entries(struct i915_address_space *vm,
-				     struct i915_vma_resource *vma_res,
-				     enum i915_cache_level cache_level,
-				     u32 unused)
-{
-	unsigned int flags = (cache_level == I915_CACHE_NONE) ?
-		AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
-
-	intel_gtt_insert_sg_entries(vma_res->bi.pages, vma_res->start >> PAGE_SHIFT,
-				    flags);
-}
-
-static void i915_ggtt_clear_range(struct i915_address_space *vm,
-				  u64 start, u64 length)
-{
-	intel_gtt_clear_range(start >> PAGE_SHIFT, length >> PAGE_SHIFT);
-}
-
-static void ggtt_bind_vma(struct i915_address_space *vm,
+void ggtt_bind_vma(struct i915_address_space *vm,
 			  struct i915_vm_pt_stash *stash,
 			  struct i915_vma_resource *vma_res,
 			  enum i915_cache_level cache_level,
@@ -521,7 +485,7 @@ static void ggtt_bind_vma(struct i915_address_space *vm,
 	vma_res->page_sizes_gtt = I915_GTT_PAGE_SIZE;
 }
 
-static void ggtt_unbind_vma(struct i915_address_space *vm,
+void ggtt_unbind_vma(struct i915_address_space *vm,
 			    struct i915_vma_resource *vma_res)
 {
 	vm->clear_range(vm, vma_res->start, vma_res->vma_size);
@@ -1149,54 +1113,6 @@ static int gen6_gmch_probe(struct i915_ggtt *ggtt)
 	return ggtt_probe_common(ggtt, size);
 }
 
-static void i915_gmch_remove(struct i915_address_space *vm)
-{
-	intel_gmch_remove();
-}
-
-static int i915_gmch_probe(struct i915_ggtt *ggtt)
-{
-	struct drm_i915_private *i915 = ggtt->vm.i915;
-	phys_addr_t gmadr_base;
-	int ret;
-
-	ret = intel_gmch_probe(i915->bridge_dev, to_pci_dev(i915->drm.dev), NULL);
-	if (!ret) {
-		drm_err(&i915->drm, "failed to set up gmch\n");
-		return -EIO;
-	}
-
-	intel_gtt_get(&ggtt->vm.total, &gmadr_base, &ggtt->mappable_end);
-
-	ggtt->gmadr =
-		(struct resource)DEFINE_RES_MEM(gmadr_base, ggtt->mappable_end);
-
-	ggtt->vm.alloc_pt_dma = alloc_pt_dma;
-	ggtt->vm.alloc_scratch_dma = alloc_pt_dma;
-
-	if (needs_idle_maps(i915)) {
-		drm_notice(&i915->drm,
-			   "Flushing DMA requests before IOMMU unmaps; performance may be degraded\n");
-		ggtt->do_idle_maps = true;
-	}
-
-	ggtt->vm.insert_page = i915_ggtt_insert_page;
-	ggtt->vm.insert_entries = i915_ggtt_insert_entries;
-	ggtt->vm.clear_range = i915_ggtt_clear_range;
-	ggtt->vm.cleanup = i915_gmch_remove;
-
-	ggtt->invalidate = gmch_ggtt_invalidate;
-
-	ggtt->vm.vma_ops.bind_vma    = ggtt_bind_vma;
-	ggtt->vm.vma_ops.unbind_vma  = ggtt_unbind_vma;
-
-	if (unlikely(ggtt->do_idle_maps))
-		drm_notice(&i915->drm,
-			   "Applying Ironlake quirks for intel_iommu\n");
-
-	return 0;
-}
-
 static int ggtt_probe_hw(struct i915_ggtt *ggtt, struct intel_gt *gt)
 {
 	struct drm_i915_private *i915 = gt->i915;
@@ -1266,10 +1182,7 @@ int i915_ggtt_probe_hw(struct drm_i915_private *i915)
 
 int i915_ggtt_enable_hw(struct drm_i915_private *i915)
 {
-	if (GRAPHICS_VER(i915) < 6 && !intel_enable_gtt())
-		return -EIO;
-
-	return 0;
+	return i915_gtt_support_enable_hw(i915);
 }
 
 void i915_ggtt_enable_guc(struct i915_ggtt *ggtt)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index 57ca1e6b6203..abdf8dc8ddf7 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -4,7 +4,6 @@
  */
 
 #include <drm/drm_managed.h>
-#include <drm/intel-gtt.h>
 
 #include "gem/i915_gem_internal.h"
 #include "gem/i915_gem_lmem.h"
@@ -20,6 +19,7 @@
 #include "intel_gt_pm.h"
 #include "intel_gt_regs.h"
 #include "intel_gt_requests.h"
+#include "intel_gtt_support.h"
 #include "intel_migrate.h"
 #include "intel_mocs.h"
 #include "intel_pm.h"
@@ -443,9 +443,7 @@ void intel_gt_flush_ggtt_writes(struct intel_gt *gt)
 
 void intel_gt_chipset_flush(struct intel_gt *gt)
 {
-	wmb();
-	if (GRAPHICS_VER(gt->i915) < 6)
-		intel_gtt_chipset_flush();
+	intel_gtt_support_chipset_flush(gt);
 }
 
 void intel_gt_driver_register(struct intel_gt *gt)
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h
index 4529b5e9f6e6..fd1dea85bde4 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
@@ -547,6 +547,14 @@ i915_page_dir_dma_addr(const struct i915_ppgtt *ppgtt, const unsigned int n)
 void ppgtt_init(struct i915_ppgtt *ppgtt, struct intel_gt *gt,
 		unsigned long lmem_pt_obj_flags);
 
+void ggtt_bind_vma(struct i915_address_space *vm,
+			  struct i915_vm_pt_stash *stash,
+			  struct i915_vma_resource *vma_res,
+			  enum i915_cache_level cache_level,
+			  u32 flags);
+void ggtt_unbind_vma(struct i915_address_space *vm,
+			    struct i915_vma_resource *vma_res);
+
 int i915_ggtt_probe_hw(struct drm_i915_private *i915);
 int i915_ggtt_init_hw(struct drm_i915_private *i915);
 int i915_ggtt_enable_hw(struct drm_i915_private *i915);
@@ -654,4 +662,6 @@ static inline struct sgt_dma {
 	return (struct sgt_dma){ sg, addr, addr + sg_dma_len(sg) };
 }
 
+bool needs_idle_maps(struct drm_i915_private *i915);
+
 #endif
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt_support.c b/drivers/gpu/drm/i915/gt/intel_gtt_support.c
new file mode 100644
index 000000000000..d6d22b1a9520
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_gtt_support.c
@@ -0,0 +1,113 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#include <drm/intel-gtt.h>
+
+#include <linux/agp_backend.h>
+
+#include "i915_drv.h"
+#include "intel_gtt_support.h"
+#include "intel_gt.h"
+
+/* Wrapper for intel_gt_chipset_flush() */
+void intel_gtt_support_chipset_flush(struct intel_gt *gt)
+{
+	wmb();
+	if (GRAPHICS_VER(gt->i915) < 6)
+		intel_gtt_chipset_flush();
+}
+
+static void gmch_ggtt_invalidate(struct i915_ggtt *ggtt)
+{
+	intel_gtt_chipset_flush();
+}
+
+static void i915_ggtt_insert_page(struct i915_address_space *vm,
+				  dma_addr_t addr,
+				  u64 offset,
+				  enum i915_cache_level cache_level,
+				  u32 unused)
+{
+	unsigned int flags = (cache_level == I915_CACHE_NONE) ?
+		AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
+
+	intel_gtt_insert_page(addr, offset >> PAGE_SHIFT, flags);
+}
+
+static void i915_ggtt_insert_entries(struct i915_address_space *vm,
+				     struct i915_vma_resource *vma_res,
+				     enum i915_cache_level cache_level,
+				     u32 unused)
+{
+	unsigned int flags = (cache_level == I915_CACHE_NONE) ?
+		AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
+
+	intel_gtt_insert_sg_entries(vma_res->bi.pages, vma_res->start >> PAGE_SHIFT,
+				    flags);
+}
+
+static void i915_ggtt_clear_range(struct i915_address_space *vm,
+					 u64 start, u64 length)
+{
+	intel_gtt_clear_range(start >> PAGE_SHIFT, length >> PAGE_SHIFT);
+}
+
+static void i915_gmch_remove(struct i915_address_space *vm)
+{
+	intel_gmch_remove();
+}
+
+/* Original i915_gmch_probe() behavior for x86 */
+int i915_gmch_probe(struct i915_ggtt *ggtt)
+{
+	struct drm_i915_private *i915 = ggtt->vm.i915;
+	phys_addr_t gmadr_base;
+	int ret;
+
+	ret = intel_gmch_probe(i915->bridge_dev, to_pci_dev(i915->drm.dev), NULL);
+	if (!ret) {
+		drm_err(&i915->drm, "failed to set up gmch\n");
+		return -EIO;
+	}
+
+	intel_gtt_get(&ggtt->vm.total, &gmadr_base, &ggtt->mappable_end);
+
+	ggtt->gmadr =
+		(struct resource)DEFINE_RES_MEM(gmadr_base, ggtt->mappable_end);
+
+	ggtt->vm.alloc_pt_dma = alloc_pt_dma;
+	ggtt->vm.alloc_scratch_dma = alloc_pt_dma;
+
+	if (needs_idle_maps(i915)) {
+		drm_notice(&i915->drm,
+			   "Flushing DMA requests before IOMMU unmaps; performance may be degraded\n");
+		ggtt->do_idle_maps = true;
+	}
+
+	ggtt->vm.insert_page = i915_ggtt_insert_page;
+	ggtt->vm.insert_entries = i915_ggtt_insert_entries;
+	ggtt->vm.clear_range = i915_ggtt_clear_range;
+	ggtt->vm.cleanup = i915_gmch_remove;
+
+	ggtt->invalidate = gmch_ggtt_invalidate;
+
+	ggtt->vm.vma_ops.bind_vma    = ggtt_bind_vma;
+	ggtt->vm.vma_ops.unbind_vma  = ggtt_unbind_vma;
+
+	if (unlikely(ggtt->do_idle_maps))
+		drm_notice(&i915->drm,
+			   "Applying Ironlake quirks for intel_iommu\n");
+
+	return 0;
+}
+
+/* Wrapper for i915_ggtt_enable_hw() */
+int i915_gtt_support_enable_hw(struct drm_i915_private *i915)
+{
+	if (GRAPHICS_VER(i915) < 6 && !intel_enable_gtt())
+		return -EIO;
+
+	return 0;
+}
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt_support.h b/drivers/gpu/drm/i915/gt/intel_gtt_support.h
new file mode 100644
index 000000000000..2ebb0dd66ad7
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_gtt_support.h
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef __INTEL_GTT_SUPPORT_H__
+#define __INTEL_GTT_SUPPORT_H__
+
+#include "intel_gtt.h"
+
+/* For x86 platforms */
+#if IS_ENABLED(CONFIG_X86)
+/* Wrapper for intel_gt_chipset_flush() */
+void intel_gtt_support_chipset_flush(struct intel_gt *gt);
+/* Original i915_gmch_probe() behavior */
+int i915_gmch_probe(struct i915_ggtt *ggtt);
+/* Wrapper for i915_ggtt_enable_hw() */
+int i915_gtt_support_enable_hw(struct drm_i915_private *i915);
+
+/* Stubs for non-x86 platforms */
+#else
+static inline void intel_gtt_support_chipset_flush(struct intel_gt *gt)
+{
+	return;
+}
+static inline int i915_gmch_probe(struct i915_ggtt *ggtt)
+{
+	/* We shouldn't detect a device in this case, return fail */
+	return -1;
+}
+
+static inline int i915_gtt_support_enable_hw(struct drm_i915_private *i915)
+{
+	/* No HW should be enabled for this case, return fail */
+	return -1;
+}
+#endif
+
+#endif /* __INTEL_GTT_SUPPORT_H__ */
-- 
2.25.1

Re: [Intel-gfx] [PATCH 2/2] drm/i915/gt: Split intel-gtt functions by arch

[Lucas De Marchi]

On Fri, Mar 18, 2022 at 07:00:42PM -0700, Casey Bowman wrote:
>Some functions defined in the intel-gtt module are used in several
>areas, but is only supported on x86 platforms.
>
>By separating these calls and their static underlying functions to
>area, we are able to compile out these functions for non-x86 builds
>and provide stubs for the non-x86 implementations.
>

I like the direction this is going now. See comments below.

>Signed-off-by: Casey Bowman <casey.g.bowman@intel.com>
>---
> drivers/gpu/drm/i915/Makefile               |   2 +
> drivers/gpu/drm/i915/gt/intel_ggtt.c        |  97 +----------------
> drivers/gpu/drm/i915/gt/intel_gt.c          |   6 +-
> drivers/gpu/drm/i915/gt/intel_gtt.h         |  10 ++
> drivers/gpu/drm/i915/gt/intel_gtt_support.c | 113 ++++++++++++++++++++
> drivers/gpu/drm/i915/gt/intel_gtt_support.h |  39 +++++++
> 6 files changed, 171 insertions(+), 96 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/gt/intel_gtt_support.c
> create mode 100644 drivers/gpu/drm/i915/gt/intel_gtt_support.h
>
>diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
>index 61b078bd1b32..cc332cb6833b 100644
>--- a/drivers/gpu/drm/i915/Makefile
>+++ b/drivers/gpu/drm/i915/Makefile
>@@ -124,6 +124,8 @@ gt-y += \
> 	gt/intel_workarounds.o \
> 	gt/shmem_utils.o \
> 	gt/sysfs_engines.o
>+# x86 intel-gtt module support
>+gt-$(CONFIG_X86) += gt/intel_gtt_support.o
> # autogenerated null render state
> gt-y += \
> 	gt/gen6_renderstate.o \
>diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
>index 04191fe2ee34..db2f1b12c273 100644
>--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
>+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
>@@ -3,14 +3,12 @@
>  * Copyright © 2020 Intel Corporation
>  */
>
>-#include <linux/agp_backend.h>
> #include <linux/stop_machine.h>
>
> #include <asm/set_memory.h>
> #include <asm/smp.h>
>
> #include <drm/i915_drm.h>
>-#include <drm/intel-gtt.h>
>
> #include "gem/i915_gem_lmem.h"
>
>@@ -21,6 +19,7 @@
> #include "i915_vgpu.h"
>
> #include "intel_gtt.h"
>+#include "intel_gtt_support.h"
> #include "gen8_ppgtt.h"
>
> static void i915_ggtt_color_adjust(const struct drm_mm_node *node,
>@@ -98,7 +97,7 @@ int i915_ggtt_init_hw(struct drm_i915_private *i915)
>  * Certain Gen5 chipsets require idling the GPU before
>  * unmapping anything from the GTT when VT-d is enabled.
>  */
>-static bool needs_idle_maps(struct drm_i915_private *i915)
>+bool needs_idle_maps(struct drm_i915_private *i915)

why didn't you move this function together? It's only used by
i915_gmch_probe()

If it was something generic that needed to be exported, you'd need to
rename it to respect the namespace.

but here I think you can just move it to the new file.

> {
> 	/*
> 	 * Query intel_iommu to see if we need the workaround. Presumably that
>@@ -229,11 +228,6 @@ static void guc_ggtt_invalidate(struct i915_ggtt *ggtt)
> 		intel_uncore_write_fw(uncore, GEN8_GTCR, GEN8_GTCR_INVALIDATE);
> }
>
>-static void gmch_ggtt_invalidate(struct i915_ggtt *ggtt)
>-{
>-	intel_gtt_chipset_flush();
>-}
>-
> u64 gen8_ggtt_pte_encode(dma_addr_t addr,
> 			 enum i915_cache_level level,
> 			 u32 flags)
>@@ -467,37 +461,7 @@ static void gen6_ggtt_clear_range(struct i915_address_space *vm,
> 		iowrite32(scratch_pte, &gtt_base[i]);
> }
>
>-static void i915_ggtt_insert_page(struct i915_address_space *vm,
>-				  dma_addr_t addr,
>-				  u64 offset,
>-				  enum i915_cache_level cache_level,
>-				  u32 unused)
>-{
>-	unsigned int flags = (cache_level == I915_CACHE_NONE) ?
>-		AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
>-
>-	intel_gtt_insert_page(addr, offset >> PAGE_SHIFT, flags);
>-}
>-
>-static void i915_ggtt_insert_entries(struct i915_address_space *vm,
>-				     struct i915_vma_resource *vma_res,
>-				     enum i915_cache_level cache_level,
>-				     u32 unused)
>-{
>-	unsigned int flags = (cache_level == I915_CACHE_NONE) ?
>-		AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
>-
>-	intel_gtt_insert_sg_entries(vma_res->bi.pages, vma_res->start >> PAGE_SHIFT,
>-				    flags);
>-}
>-
>-static void i915_ggtt_clear_range(struct i915_address_space *vm,
>-				  u64 start, u64 length)
>-{
>-	intel_gtt_clear_range(start >> PAGE_SHIFT, length >> PAGE_SHIFT);
>-}
>-
>-static void ggtt_bind_vma(struct i915_address_space *vm,
>+void ggtt_bind_vma(struct i915_address_space *vm,
> 			  struct i915_vm_pt_stash *stash,
> 			  struct i915_vma_resource *vma_res,
> 			  enum i915_cache_level cache_level,
>@@ -521,7 +485,7 @@ static void ggtt_bind_vma(struct i915_address_space *vm,
> 	vma_res->page_sizes_gtt = I915_GTT_PAGE_SIZE;
> }
>
>-static void ggtt_unbind_vma(struct i915_address_space *vm,
>+void ggtt_unbind_vma(struct i915_address_space *vm,
> 			    struct i915_vma_resource *vma_res)
> {
> 	vm->clear_range(vm, vma_res->start, vma_res->vma_size);
>@@ -1149,54 +1113,6 @@ static int gen6_gmch_probe(struct i915_ggtt *ggtt)
> 	return ggtt_probe_common(ggtt, size);
> }
>
>-static void i915_gmch_remove(struct i915_address_space *vm)
>-{
>-	intel_gmch_remove();
>-}
>-
>-static int i915_gmch_probe(struct i915_ggtt *ggtt)
>-{
>-	struct drm_i915_private *i915 = ggtt->vm.i915;
>-	phys_addr_t gmadr_base;
>-	int ret;
>-
>-	ret = intel_gmch_probe(i915->bridge_dev, to_pci_dev(i915->drm.dev), NULL);
>-	if (!ret) {
>-		drm_err(&i915->drm, "failed to set up gmch\n");
>-		return -EIO;
>-	}
>-
>-	intel_gtt_get(&ggtt->vm.total, &gmadr_base, &ggtt->mappable_end);
>-
>-	ggtt->gmadr =
>-		(struct resource)DEFINE_RES_MEM(gmadr_base, ggtt->mappable_end);
>-
>-	ggtt->vm.alloc_pt_dma = alloc_pt_dma;
>-	ggtt->vm.alloc_scratch_dma = alloc_pt_dma;
>-
>-	if (needs_idle_maps(i915)) {
>-		drm_notice(&i915->drm,
>-			   "Flushing DMA requests before IOMMU unmaps; performance may be degraded\n");
>-		ggtt->do_idle_maps = true;
>-	}
>-
>-	ggtt->vm.insert_page = i915_ggtt_insert_page;
>-	ggtt->vm.insert_entries = i915_ggtt_insert_entries;
>-	ggtt->vm.clear_range = i915_ggtt_clear_range;
>-	ggtt->vm.cleanup = i915_gmch_remove;
>-
>-	ggtt->invalidate = gmch_ggtt_invalidate;
>-
>-	ggtt->vm.vma_ops.bind_vma    = ggtt_bind_vma;
>-	ggtt->vm.vma_ops.unbind_vma  = ggtt_unbind_vma;
>-
>-	if (unlikely(ggtt->do_idle_maps))
>-		drm_notice(&i915->drm,
>-			   "Applying Ironlake quirks for intel_iommu\n");
>-
>-	return 0;
>-}
>-
> static int ggtt_probe_hw(struct i915_ggtt *ggtt, struct intel_gt *gt)
> {
> 	struct drm_i915_private *i915 = gt->i915;
>@@ -1266,10 +1182,7 @@ int i915_ggtt_probe_hw(struct drm_i915_private *i915)
>
> int i915_ggtt_enable_hw(struct drm_i915_private *i915)
> {
>-	if (GRAPHICS_VER(i915) < 6 && !intel_enable_gtt())
>-		return -EIO;
>-
>-	return 0;
>+	return i915_gtt_support_enable_hw(i915);
> }
>
> void i915_ggtt_enable_guc(struct i915_ggtt *ggtt)
>diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
>index 57ca1e6b6203..abdf8dc8ddf7 100644
>--- a/drivers/gpu/drm/i915/gt/intel_gt.c
>+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
>@@ -4,7 +4,6 @@
>  */
>
> #include <drm/drm_managed.h>
>-#include <drm/intel-gtt.h>
>
> #include "gem/i915_gem_internal.h"
> #include "gem/i915_gem_lmem.h"
>@@ -20,6 +19,7 @@
> #include "intel_gt_pm.h"
> #include "intel_gt_regs.h"
> #include "intel_gt_requests.h"
>+#include "intel_gtt_support.h"
> #include "intel_migrate.h"
> #include "intel_mocs.h"
> #include "intel_pm.h"
>@@ -443,9 +443,7 @@ void intel_gt_flush_ggtt_writes(struct intel_gt *gt)
>
> void intel_gt_chipset_flush(struct intel_gt *gt)
> {
>-	wmb();
>-	if (GRAPHICS_VER(gt->i915) < 6)
>-		intel_gtt_chipset_flush();
>+	intel_gtt_support_chipset_flush(gt);

humn... 2 things here:

1) intel_gtt_support_* may not be a good name. Here it seems the
function would return a boolean saying if chipset flush is supported.

Also, all the functions in intel_gtt_support_* are actually about
support the i915 graphics card (not to be confused is i915, the name of
the module). intel_gtt_* clashes with the other module. So, looking at
the calls I'd actually call these e.g. gen5_gtt_chipset_flush()

This would follow what is done in other headers/sources like
gen*_renderstate.*, gen*_ppgtt.*, etc

Then this function would become like:

void intel_gt_chipset_flush(struct intel_gt *gt)
{
	wmb();
	if (GRAPHICS_VER(gt->i915) <= 5)
		gen5_gtt_chipset_flush();
}

So we split what is to be done for every gpu (the wmb()) from what is to
be done for the older gens.


What do you think? Jani / Matt?


> }
>
> void intel_gt_driver_register(struct intel_gt *gt)
>diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h
>index 4529b5e9f6e6..fd1dea85bde4 100644
>--- a/drivers/gpu/drm/i915/gt/intel_gtt.h
>+++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
>@@ -547,6 +547,14 @@ i915_page_dir_dma_addr(const struct i915_ppgtt *ppgtt, const unsigned int n)
> void ppgtt_init(struct i915_ppgtt *ppgtt, struct intel_gt *gt,
> 		unsigned long lmem_pt_obj_flags);
>
>+void ggtt_bind_vma(struct i915_address_space *vm,
>+			  struct i915_vm_pt_stash *stash,
>+			  struct i915_vma_resource *vma_res,
>+			  enum i915_cache_level cache_level,
>+			  u32 flags);
>+void ggtt_unbind_vma(struct i915_address_space *vm,
>+			    struct i915_vma_resource *vma_res);
>+
> int i915_ggtt_probe_hw(struct drm_i915_private *i915);
> int i915_ggtt_init_hw(struct drm_i915_private *i915);
> int i915_ggtt_enable_hw(struct drm_i915_private *i915);
>@@ -654,4 +662,6 @@ static inline struct sgt_dma {
> 	return (struct sgt_dma){ sg, addr, addr + sg_dma_len(sg) };
> }
>
>+bool needs_idle_maps(struct drm_i915_private *i915);
>+
> #endif
>diff --git a/drivers/gpu/drm/i915/gt/intel_gtt_support.c b/drivers/gpu/drm/i915/gt/intel_gtt_support.c
>new file mode 100644
>index 000000000000..d6d22b1a9520
>--- /dev/null
>+++ b/drivers/gpu/drm/i915/gt/intel_gtt_support.c
>@@ -0,0 +1,113 @@
>+// SPDX-License-Identifier: MIT
>+/*
>+ * Copyright © 2022 Intel Corporation
>+ */
>+
>+#include <drm/intel-gtt.h>
>+
>+#include <linux/agp_backend.h>
>+
>+#include "i915_drv.h"
>+#include "intel_gtt_support.h"
>+#include "intel_gt.h"
>+
>+/* Wrapper for intel_gt_chipset_flush() */
>+void intel_gtt_support_chipset_flush(struct intel_gt *gt)
>+{
>+	wmb();
>+	if (GRAPHICS_VER(gt->i915) < 6)
>+		intel_gtt_chipset_flush();
>+}
>+
>+static void gmch_ggtt_invalidate(struct i915_ggtt *ggtt)
>+{
>+	intel_gtt_chipset_flush();
>+}
>+
>+static void i915_ggtt_insert_page(struct i915_address_space *vm,
>+				  dma_addr_t addr,
>+				  u64 offset,
>+				  enum i915_cache_level cache_level,
>+				  u32 unused)
>+{
>+	unsigned int flags = (cache_level == I915_CACHE_NONE) ?
>+		AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
>+
>+	intel_gtt_insert_page(addr, offset >> PAGE_SHIFT, flags);
>+}
>+
>+static void i915_ggtt_insert_entries(struct i915_address_space *vm,
>+				     struct i915_vma_resource *vma_res,
>+				     enum i915_cache_level cache_level,
>+				     u32 unused)
>+{
>+	unsigned int flags = (cache_level == I915_CACHE_NONE) ?
>+		AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
>+
>+	intel_gtt_insert_sg_entries(vma_res->bi.pages, vma_res->start >> PAGE_SHIFT,
>+				    flags);
>+}
>+
>+static void i915_ggtt_clear_range(struct i915_address_space *vm,
>+					 u64 start, u64 length)
>+{
>+	intel_gtt_clear_range(start >> PAGE_SHIFT, length >> PAGE_SHIFT);
>+}
>+
>+static void i915_gmch_remove(struct i915_address_space *vm)
>+{
>+	intel_gmch_remove();
>+}
>+
>+/* Original i915_gmch_probe() behavior for x86 */
>+int i915_gmch_probe(struct i915_ggtt *ggtt)
>+{
>+	struct drm_i915_private *i915 = ggtt->vm.i915;
>+	phys_addr_t gmadr_base;
>+	int ret;
>+
>+	ret = intel_gmch_probe(i915->bridge_dev, to_pci_dev(i915->drm.dev), NULL);
>+	if (!ret) {
>+		drm_err(&i915->drm, "failed to set up gmch\n");
>+		return -EIO;
>+	}
>+
>+	intel_gtt_get(&ggtt->vm.total, &gmadr_base, &ggtt->mappable_end);
>+
>+	ggtt->gmadr =
>+		(struct resource)DEFINE_RES_MEM(gmadr_base, ggtt->mappable_end);
>+
>+	ggtt->vm.alloc_pt_dma = alloc_pt_dma;
>+	ggtt->vm.alloc_scratch_dma = alloc_pt_dma;
>+
>+	if (needs_idle_maps(i915)) {
>+		drm_notice(&i915->drm,
>+			   "Flushing DMA requests before IOMMU unmaps; performance may be degraded\n");
>+		ggtt->do_idle_maps = true;
>+	}
>+
>+	ggtt->vm.insert_page = i915_ggtt_insert_page;
>+	ggtt->vm.insert_entries = i915_ggtt_insert_entries;
>+	ggtt->vm.clear_range = i915_ggtt_clear_range;
>+	ggtt->vm.cleanup = i915_gmch_remove;
>+
>+	ggtt->invalidate = gmch_ggtt_invalidate;
>+
>+	ggtt->vm.vma_ops.bind_vma    = ggtt_bind_vma;
>+	ggtt->vm.vma_ops.unbind_vma  = ggtt_unbind_vma;
>+
>+	if (unlikely(ggtt->do_idle_maps))
>+		drm_notice(&i915->drm,
>+			   "Applying Ironlake quirks for intel_iommu\n");
>+
>+	return 0;
>+}
>+
>+/* Wrapper for i915_ggtt_enable_hw() */
>+int i915_gtt_support_enable_hw(struct drm_i915_private *i915)
>+{
>+	if (GRAPHICS_VER(i915) < 6 && !intel_enable_gtt())
>+		return -EIO;
>+
>+	return 0;
>+}
>diff --git a/drivers/gpu/drm/i915/gt/intel_gtt_support.h b/drivers/gpu/drm/i915/gt/intel_gtt_support.h
>new file mode 100644
>index 000000000000..2ebb0dd66ad7
>--- /dev/null
>+++ b/drivers/gpu/drm/i915/gt/intel_gtt_support.h
>@@ -0,0 +1,39 @@
>+/* SPDX-License-Identifier: MIT */
>+/*
>+ * Copyright © 2022 Intel Corporation
>+ */
>+
>+#ifndef __INTEL_GTT_SUPPORT_H__
>+#define __INTEL_GTT_SUPPORT_H__
>+
>+#include "intel_gtt.h"
>+
>+/* For x86 platforms */
>+#if IS_ENABLED(CONFIG_X86)
>+/* Wrapper for intel_gt_chipset_flush() */
>+void intel_gtt_support_chipset_flush(struct intel_gt *gt);
>+/* Original i915_gmch_probe() behavior */
>+int i915_gmch_probe(struct i915_ggtt *ggtt);
>+/* Wrapper for i915_ggtt_enable_hw() */
>+int i915_gtt_support_enable_hw(struct drm_i915_private *i915);
>+


we are trying to standardize on:

this_is_a_namespace.c / this_is_a_namespace.h

and the functions exported are:

this_is_a_namespace_*

Here you have 3 functions, all with different prefixes:

intel_gtt_support_
i915_gmch_
i915_ggtt_

we need to rename the functions we export. If people think my suggestion
above with gen5_gtt_* is a good one, then this would be the namespace
for all of them

I think we are now much closer to a version to be merged.

thanks,
Lucas De Marchi

>+/* Stubs for non-x86 platforms */
>+#else
>+static inline void intel_gtt_support_chipset_flush(struct intel_gt *gt)
>+{
>+	return;
>+}
>+static inline int i915_gmch_probe(struct i915_ggtt *ggtt)
>+{
>+	/* We shouldn't detect a device in this case, return fail */
>+	return -1;
>+}
>+
>+static inline int i915_gtt_support_enable_hw(struct drm_i915_private *i915)
>+{
>+	/* No HW should be enabled for this case, return fail */
>+	return -1;
>+}
>+#endif
>+
>+#endif /* __INTEL_GTT_SUPPORT_H__ */
>-- 
>2.25.1
>

Re: [Intel-gfx] [PATCH 2/2] drm/i915/gt: Split intel-gtt functions by arch

[Casey Bowman]

On 3/18/22 20:39, Lucas De Marchi wrote:
> On Fri, Mar 18, 2022 at 07:00:42PM -0700, Casey Bowman wrote:
>> Some functions defined in the intel-gtt module are used in several
>> areas, but is only supported on x86 platforms.
>>
>> By separating these calls and their static underlying functions to
>> area, we are able to compile out these functions for non-x86 builds
>> and provide stubs for the non-x86 implementations.
>>
>
> I like the direction this is going now. See comments below.
>
>> Signed-off-by: Casey Bowman <casey.g.bowman@intel.com>
>> ---
>> drivers/gpu/drm/i915/Makefile               |   2 +
>> drivers/gpu/drm/i915/gt/intel_ggtt.c        |  97 +----------------
>> drivers/gpu/drm/i915/gt/intel_gt.c          |   6 +-
>> drivers/gpu/drm/i915/gt/intel_gtt.h         |  10 ++
>> drivers/gpu/drm/i915/gt/intel_gtt_support.c | 113 ++++++++++++++++++++
>> drivers/gpu/drm/i915/gt/intel_gtt_support.h |  39 +++++++
>> 6 files changed, 171 insertions(+), 96 deletions(-)
>> create mode 100644 drivers/gpu/drm/i915/gt/intel_gtt_support.c
>> create mode 100644 drivers/gpu/drm/i915/gt/intel_gtt_support.h
>>
>> diff --git a/drivers/gpu/drm/i915/Makefile 
>> b/drivers/gpu/drm/i915/Makefile
>> index 61b078bd1b32..cc332cb6833b 100644
>> --- a/drivers/gpu/drm/i915/Makefile
>> +++ b/drivers/gpu/drm/i915/Makefile
>> @@ -124,6 +124,8 @@ gt-y += \
>>     gt/intel_workarounds.o \
>>     gt/shmem_utils.o \
>>     gt/sysfs_engines.o
>> +# x86 intel-gtt module support
>> +gt-$(CONFIG_X86) += gt/intel_gtt_support.o
>> # autogenerated null render state
>> gt-y += \
>>     gt/gen6_renderstate.o \
>> diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c 
>> b/drivers/gpu/drm/i915/gt/intel_ggtt.c
>> index 04191fe2ee34..db2f1b12c273 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
>> @@ -3,14 +3,12 @@
>>  * Copyright © 2020 Intel Corporation
>>  */
>>
>> -#include <linux/agp_backend.h>
>> #include <linux/stop_machine.h>
>>
>> #include <asm/set_memory.h>
>> #include <asm/smp.h>
>>
>> #include <drm/i915_drm.h>
>> -#include <drm/intel-gtt.h>
>>
>> #include "gem/i915_gem_lmem.h"
>>
>> @@ -21,6 +19,7 @@
>> #include "i915_vgpu.h"
>>
>> #include "intel_gtt.h"
>> +#include "intel_gtt_support.h"
>> #include "gen8_ppgtt.h"
>>
>> static void i915_ggtt_color_adjust(const struct drm_mm_node *node,
>> @@ -98,7 +97,7 @@ int i915_ggtt_init_hw(struct drm_i915_private *i915)
>>  * Certain Gen5 chipsets require idling the GPU before
>>  * unmapping anything from the GTT when VT-d is enabled.
>>  */
>> -static bool needs_idle_maps(struct drm_i915_private *i915)
>> +bool needs_idle_maps(struct drm_i915_private *i915)
>
> why didn't you move this function together? It's only used by
> i915_gmch_probe()
>
> If it was something generic that needed to be exported, you'd need to
> rename it to respect the namespace.
>
> but here I think you can just move it to the new file.

Yeah, I think this was an oversight on my part when moving the
various files only associated with i915_gmch_probe(), for some
reason, I assume I thought that this was part of the other
*_gmch_probe() calls.

This will be moved as the others were in v2.

>
>> {
>>     /*
>>      * Query intel_iommu to see if we need the workaround. Presumably 
>> that
>> @@ -229,11 +228,6 @@ static void guc_ggtt_invalidate(struct i915_ggtt 
>> *ggtt)
>>         intel_uncore_write_fw(uncore, GEN8_GTCR, GEN8_GTCR_INVALIDATE);
>> }
>>
>> -static void gmch_ggtt_invalidate(struct i915_ggtt *ggtt)
>> -{
>> -    intel_gtt_chipset_flush();
>> -}
>> -
>> u64 gen8_ggtt_pte_encode(dma_addr_t addr,
>>              enum i915_cache_level level,
>>              u32 flags)
>> @@ -467,37 +461,7 @@ static void gen6_ggtt_clear_range(struct 
>> i915_address_space *vm,
>>         iowrite32(scratch_pte, &gtt_base[i]);
>> }
>>
>> -static void i915_ggtt_insert_page(struct i915_address_space *vm,
>> -                  dma_addr_t addr,
>> -                  u64 offset,
>> -                  enum i915_cache_level cache_level,
>> -                  u32 unused)
>> -{
>> -    unsigned int flags = (cache_level == I915_CACHE_NONE) ?
>> -        AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
>> -
>> -    intel_gtt_insert_page(addr, offset >> PAGE_SHIFT, flags);
>> -}
>> -
>> -static void i915_ggtt_insert_entries(struct i915_address_space *vm,
>> -                     struct i915_vma_resource *vma_res,
>> -                     enum i915_cache_level cache_level,
>> -                     u32 unused)
>> -{
>> -    unsigned int flags = (cache_level == I915_CACHE_NONE) ?
>> -        AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
>> -
>> -    intel_gtt_insert_sg_entries(vma_res->bi.pages, vma_res->start >> 
>> PAGE_SHIFT,
>> -                    flags);
>> -}
>> -
>> -static void i915_ggtt_clear_range(struct i915_address_space *vm,
>> -                  u64 start, u64 length)
>> -{
>> -    intel_gtt_clear_range(start >> PAGE_SHIFT, length >> PAGE_SHIFT);
>> -}
>> -
>> -static void ggtt_bind_vma(struct i915_address_space *vm,
>> +void ggtt_bind_vma(struct i915_address_space *vm,
>>               struct i915_vm_pt_stash *stash,
>>               struct i915_vma_resource *vma_res,
>>               enum i915_cache_level cache_level,
>> @@ -521,7 +485,7 @@ static void ggtt_bind_vma(struct 
>> i915_address_space *vm,
>>     vma_res->page_sizes_gtt = I915_GTT_PAGE_SIZE;
>> }
>>
>> -static void ggtt_unbind_vma(struct i915_address_space *vm,
>> +void ggtt_unbind_vma(struct i915_address_space *vm,
>>                 struct i915_vma_resource *vma_res)
>> {
>>     vm->clear_range(vm, vma_res->start, vma_res->vma_size);
>> @@ -1149,54 +1113,6 @@ static int gen6_gmch_probe(struct i915_ggtt 
>> *ggtt)
>>     return ggtt_probe_common(ggtt, size);
>> }
>>
>> -static void i915_gmch_remove(struct i915_address_space *vm)
>> -{
>> -    intel_gmch_remove();
>> -}
>> -
>> -static int i915_gmch_probe(struct i915_ggtt *ggtt)
>> -{
>> -    struct drm_i915_private *i915 = ggtt->vm.i915;
>> -    phys_addr_t gmadr_base;
>> -    int ret;
>> -
>> -    ret = intel_gmch_probe(i915->bridge_dev, 
>> to_pci_dev(i915->drm.dev), NULL);
>> -    if (!ret) {
>> -        drm_err(&i915->drm, "failed to set up gmch\n");
>> -        return -EIO;
>> -    }
>> -
>> -    intel_gtt_get(&ggtt->vm.total, &gmadr_base, &ggtt->mappable_end);
>> -
>> -    ggtt->gmadr =
>> -        (struct resource)DEFINE_RES_MEM(gmadr_base, 
>> ggtt->mappable_end);
>> -
>> -    ggtt->vm.alloc_pt_dma = alloc_pt_dma;
>> -    ggtt->vm.alloc_scratch_dma = alloc_pt_dma;
>> -
>> -    if (needs_idle_maps(i915)) {
>> -        drm_notice(&i915->drm,
>> -               "Flushing DMA requests before IOMMU unmaps; 
>> performance may be degraded\n");
>> -        ggtt->do_idle_maps = true;
>> -    }
>> -
>> -    ggtt->vm.insert_page = i915_ggtt_insert_page;
>> -    ggtt->vm.insert_entries = i915_ggtt_insert_entries;
>> -    ggtt->vm.clear_range = i915_ggtt_clear_range;
>> -    ggtt->vm.cleanup = i915_gmch_remove;
>> -
>> -    ggtt->invalidate = gmch_ggtt_invalidate;
>> -
>> -    ggtt->vm.vma_ops.bind_vma    = ggtt_bind_vma;
>> -    ggtt->vm.vma_ops.unbind_vma  = ggtt_unbind_vma;
>> -
>> -    if (unlikely(ggtt->do_idle_maps))
>> -        drm_notice(&i915->drm,
>> -               "Applying Ironlake quirks for intel_iommu\n");
>> -
>> -    return 0;
>> -}
>> -
>> static int ggtt_probe_hw(struct i915_ggtt *ggtt, struct intel_gt *gt)
>> {
>>     struct drm_i915_private *i915 = gt->i915;
>> @@ -1266,10 +1182,7 @@ int i915_ggtt_probe_hw(struct drm_i915_private 
>> *i915)
>>
>> int i915_ggtt_enable_hw(struct drm_i915_private *i915)
>> {
>> -    if (GRAPHICS_VER(i915) < 6 && !intel_enable_gtt())
>> -        return -EIO;
>> -
>> -    return 0;
>> +    return i915_gtt_support_enable_hw(i915);
>> }
>>
>> void i915_ggtt_enable_guc(struct i915_ggtt *ggtt)
>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c 
>> b/drivers/gpu/drm/i915/gt/intel_gt.c
>> index 57ca1e6b6203..abdf8dc8ddf7 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
>> @@ -4,7 +4,6 @@
>>  */
>>
>> #include <drm/drm_managed.h>
>> -#include <drm/intel-gtt.h>
>>
>> #include "gem/i915_gem_internal.h"
>> #include "gem/i915_gem_lmem.h"
>> @@ -20,6 +19,7 @@
>> #include "intel_gt_pm.h"
>> #include "intel_gt_regs.h"
>> #include "intel_gt_requests.h"
>> +#include "intel_gtt_support.h"
>> #include "intel_migrate.h"
>> #include "intel_mocs.h"
>> #include "intel_pm.h"
>> @@ -443,9 +443,7 @@ void intel_gt_flush_ggtt_writes(struct intel_gt *gt)
>>
>> void intel_gt_chipset_flush(struct intel_gt *gt)
>> {
>> -    wmb();
>> -    if (GRAPHICS_VER(gt->i915) < 6)
>> -        intel_gtt_chipset_flush();
>> +    intel_gtt_support_chipset_flush(gt);
>
> humn... 2 things here:
>
> 1) intel_gtt_support_* may not be a good name. Here it seems the
> function would return a boolean saying if chipset flush is supported.

Agreed, I thought it may somewhat align, but could also cause confusion,
so a discussion for a better name is likely needed.

>
> Also, all the functions in intel_gtt_support_* are actually about
> support the i915 graphics card (not to be confused is i915, the name of
> the module). intel_gtt_* clashes with the other module. So, looking at
> the calls I'd actually call these e.g. gen5_gtt_chipset_flush()
>

This seems fine with me

> This would follow what is done in other headers/sources like
> gen*_renderstate.*, gen*_ppgtt.*, etc
>
> Then this function would become like:
>
> void intel_gt_chipset_flush(struct intel_gt *gt)
> {
>     wmb();
>     if (GRAPHICS_VER(gt->i915) <= 5)
>         gen5_gtt_chipset_flush();
> }
>
> So we split what is to be done for every gpu (the wmb()) from what is to
> be done for the older gens.
>
>
> What do you think? Jani / Matt?
>
>
>> }
>>
>> void intel_gt_driver_register(struct intel_gt *gt)
>> diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h 
>> b/drivers/gpu/drm/i915/gt/intel_gtt.h
>> index 4529b5e9f6e6..fd1dea85bde4 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_gtt.h
>> +++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
>> @@ -547,6 +547,14 @@ i915_page_dir_dma_addr(const struct i915_ppgtt 
>> *ppgtt, const unsigned int n)
>> void ppgtt_init(struct i915_ppgtt *ppgtt, struct intel_gt *gt,
>>         unsigned long lmem_pt_obj_flags);
>>
>> +void ggtt_bind_vma(struct i915_address_space *vm,
>> +              struct i915_vm_pt_stash *stash,
>> +              struct i915_vma_resource *vma_res,
>> +              enum i915_cache_level cache_level,
>> +              u32 flags);
>> +void ggtt_unbind_vma(struct i915_address_space *vm,
>> +                struct i915_vma_resource *vma_res);
>> +
>> int i915_ggtt_probe_hw(struct drm_i915_private *i915);
>> int i915_ggtt_init_hw(struct drm_i915_private *i915);
>> int i915_ggtt_enable_hw(struct drm_i915_private *i915);
>> @@ -654,4 +662,6 @@ static inline struct sgt_dma {
>>     return (struct sgt_dma){ sg, addr, addr + sg_dma_len(sg) };
>> }
>>
>> +bool needs_idle_maps(struct drm_i915_private *i915);
>> +
>> #endif
>> diff --git a/drivers/gpu/drm/i915/gt/intel_gtt_support.c 
>> b/drivers/gpu/drm/i915/gt/intel_gtt_support.c
>> new file mode 100644
>> index 000000000000..d6d22b1a9520
>> --- /dev/null
>> +++ b/drivers/gpu/drm/i915/gt/intel_gtt_support.c
>> @@ -0,0 +1,113 @@
>> +// SPDX-License-Identifier: MIT
>> +/*
>> + * Copyright © 2022 Intel Corporation
>> + */
>> +
>> +#include <drm/intel-gtt.h>
>> +
>> +#include <linux/agp_backend.h>
>> +
>> +#include "i915_drv.h"
>> +#include "intel_gtt_support.h"
>> +#include "intel_gt.h"
>> +
>> +/* Wrapper for intel_gt_chipset_flush() */
>> +void intel_gtt_support_chipset_flush(struct intel_gt *gt)
>> +{
>> +    wmb();
>> +    if (GRAPHICS_VER(gt->i915) < 6)
>> +        intel_gtt_chipset_flush();
>> +}
>> +
>> +static void gmch_ggtt_invalidate(struct i915_ggtt *ggtt)
>> +{
>> +    intel_gtt_chipset_flush();
>> +}
>> +
>> +static void i915_ggtt_insert_page(struct i915_address_space *vm,
>> +                  dma_addr_t addr,
>> +                  u64 offset,
>> +                  enum i915_cache_level cache_level,
>> +                  u32 unused)
>> +{
>> +    unsigned int flags = (cache_level == I915_CACHE_NONE) ?
>> +        AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
>> +
>> +    intel_gtt_insert_page(addr, offset >> PAGE_SHIFT, flags);
>> +}
>> +
>> +static void i915_ggtt_insert_entries(struct i915_address_space *vm,
>> +                     struct i915_vma_resource *vma_res,
>> +                     enum i915_cache_level cache_level,
>> +                     u32 unused)
>> +{
>> +    unsigned int flags = (cache_level == I915_CACHE_NONE) ?
>> +        AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
>> +
>> +    intel_gtt_insert_sg_entries(vma_res->bi.pages, vma_res->start >> 
>> PAGE_SHIFT,
>> +                    flags);
>> +}
>> +
>> +static void i915_ggtt_clear_range(struct i915_address_space *vm,
>> +                     u64 start, u64 length)
>> +{
>> +    intel_gtt_clear_range(start >> PAGE_SHIFT, length >> PAGE_SHIFT);
>> +}
>> +
>> +static void i915_gmch_remove(struct i915_address_space *vm)
>> +{
>> +    intel_gmch_remove();
>> +}
>> +
>> +/* Original i915_gmch_probe() behavior for x86 */
>> +int i915_gmch_probe(struct i915_ggtt *ggtt)
>> +{
>> +    struct drm_i915_private *i915 = ggtt->vm.i915;
>> +    phys_addr_t gmadr_base;
>> +    int ret;
>> +
>> +    ret = intel_gmch_probe(i915->bridge_dev, 
>> to_pci_dev(i915->drm.dev), NULL);
>> +    if (!ret) {
>> +        drm_err(&i915->drm, "failed to set up gmch\n");
>> +        return -EIO;
>> +    }
>> +
>> +    intel_gtt_get(&ggtt->vm.total, &gmadr_base, &ggtt->mappable_end);
>> +
>> +    ggtt->gmadr =
>> +        (struct resource)DEFINE_RES_MEM(gmadr_base, 
>> ggtt->mappable_end);
>> +
>> +    ggtt->vm.alloc_pt_dma = alloc_pt_dma;
>> +    ggtt->vm.alloc_scratch_dma = alloc_pt_dma;
>> +
>> +    if (needs_idle_maps(i915)) {
>> +        drm_notice(&i915->drm,
>> +               "Flushing DMA requests before IOMMU unmaps; 
>> performance may be degraded\n");
>> +        ggtt->do_idle_maps = true;
>> +    }
>> +
>> +    ggtt->vm.insert_page = i915_ggtt_insert_page;
>> +    ggtt->vm.insert_entries = i915_ggtt_insert_entries;
>> +    ggtt->vm.clear_range = i915_ggtt_clear_range;
>> +    ggtt->vm.cleanup = i915_gmch_remove;
>> +
>> +    ggtt->invalidate = gmch_ggtt_invalidate;
>> +
>> +    ggtt->vm.vma_ops.bind_vma    = ggtt_bind_vma;
>> +    ggtt->vm.vma_ops.unbind_vma  = ggtt_unbind_vma;
>> +
>> +    if (unlikely(ggtt->do_idle_maps))
>> +        drm_notice(&i915->drm,
>> +               "Applying Ironlake quirks for intel_iommu\n");
>> +
>> +    return 0;
>> +}
>> +
>> +/* Wrapper for i915_ggtt_enable_hw() */
>> +int i915_gtt_support_enable_hw(struct drm_i915_private *i915)
>> +{
>> +    if (GRAPHICS_VER(i915) < 6 && !intel_enable_gtt())
>> +        return -EIO;
>> +
>> +    return 0;
>> +}
>> diff --git a/drivers/gpu/drm/i915/gt/intel_gtt_support.h 
>> b/drivers/gpu/drm/i915/gt/intel_gtt_support.h
>> new file mode 100644
>> index 000000000000..2ebb0dd66ad7
>> --- /dev/null
>> +++ b/drivers/gpu/drm/i915/gt/intel_gtt_support.h
>> @@ -0,0 +1,39 @@
>> +/* SPDX-License-Identifier: MIT */
>> +/*
>> + * Copyright © 2022 Intel Corporation
>> + */
>> +
>> +#ifndef __INTEL_GTT_SUPPORT_H__
>> +#define __INTEL_GTT_SUPPORT_H__
>> +
>> +#include "intel_gtt.h"
>> +
>> +/* For x86 platforms */
>> +#if IS_ENABLED(CONFIG_X86)
>> +/* Wrapper for intel_gt_chipset_flush() */
>> +void intel_gtt_support_chipset_flush(struct intel_gt *gt);
>> +/* Original i915_gmch_probe() behavior */
>> +int i915_gmch_probe(struct i915_ggtt *ggtt);
>> +/* Wrapper for i915_ggtt_enable_hw() */
>> +int i915_gtt_support_enable_hw(struct drm_i915_private *i915);
>> +
>
>
> we are trying to standardize on:
>
> this_is_a_namespace.c / this_is_a_namespace.h
>
> and the functions exported are:
>
> this_is_a_namespace_*
>
> Here you have 3 functions, all with different prefixes:
>
> intel_gtt_support_
> i915_gmch_
> i915_ggtt_
>
> we need to rename the functions we export. If people think my suggestion
> above with gen5_gtt_* is a good one, then this would be the namespace
> for all of them
>

Ok, I'll have the changes prepped for when others give their thoughts on
the name changes.

> I think we are now much closer to a version to be merged.

Thank you very much for the early review on a late Friday!
Enjoy your weekend! :)

Regards,
Casey

>
> thanks,
> Lucas De Marchi
>
>> +/* Stubs for non-x86 platforms */
>> +#else
>> +static inline void intel_gtt_support_chipset_flush(struct intel_gt *gt)
>> +{
>> +    return;
>> +}
>> +static inline int i915_gmch_probe(struct i915_ggtt *ggtt)
>> +{
>> +    /* We shouldn't detect a device in this case, return fail */
>> +    return -1;
>> +}
>> +
>> +static inline int i915_gtt_support_enable_hw(struct drm_i915_private 
>> *i915)
>> +{
>> +    /* No HW should be enabled for this case, return fail */
>> +    return -1;
>> +}
>> +#endif
>> +
>> +#endif /* __INTEL_GTT_SUPPORT_H__ */
>> -- 
>> 2.25.1
>>

Re: [Intel-gfx] [PATCH 2/2] drm/i915/gt: Split intel-gtt functions by arch

[Tvrtko Ursulin]

On 19/03/2022 03:39, Lucas De Marchi wrote:
> On Fri, Mar 18, 2022 at 07:00:42PM -0700, Casey Bowman wrote:
>> Some functions defined in the intel-gtt module are used in several
>> areas, but is only supported on x86 platforms.
>>
>> By separating these calls and their static underlying functions to
>> area, we are able to compile out these functions for non-x86 builds
>> and provide stubs for the non-x86 implementations.
>>
> 
> I like the direction this is going now. See comments below.
> 
>> Signed-off-by: Casey Bowman <casey.g.bowman@intel.com>
>> ---
>> drivers/gpu/drm/i915/Makefile               |   2 +
>> drivers/gpu/drm/i915/gt/intel_ggtt.c        |  97 +----------------
>> drivers/gpu/drm/i915/gt/intel_gt.c          |   6 +-
>> drivers/gpu/drm/i915/gt/intel_gtt.h         |  10 ++
>> drivers/gpu/drm/i915/gt/intel_gtt_support.c | 113 ++++++++++++++++++++
>> drivers/gpu/drm/i915/gt/intel_gtt_support.h |  39 +++++++
>> 6 files changed, 171 insertions(+), 96 deletions(-)
>> create mode 100644 drivers/gpu/drm/i915/gt/intel_gtt_support.c
>> create mode 100644 drivers/gpu/drm/i915/gt/intel_gtt_support.h
>>
>> diff --git a/drivers/gpu/drm/i915/Makefile 
>> b/drivers/gpu/drm/i915/Makefile
>> index 61b078bd1b32..cc332cb6833b 100644
>> --- a/drivers/gpu/drm/i915/Makefile
>> +++ b/drivers/gpu/drm/i915/Makefile
>> @@ -124,6 +124,8 @@ gt-y += \
>>     gt/intel_workarounds.o \
>>     gt/shmem_utils.o \
>>     gt/sysfs_engines.o
>> +# x86 intel-gtt module support
>> +gt-$(CONFIG_X86) += gt/intel_gtt_support.o
>> # autogenerated null render state
>> gt-y += \
>>     gt/gen6_renderstate.o \
>> diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c 
>> b/drivers/gpu/drm/i915/gt/intel_ggtt.c
>> index 04191fe2ee34..db2f1b12c273 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
>> @@ -3,14 +3,12 @@
>>  * Copyright © 2020 Intel Corporation
>>  */
>>
>> -#include <linux/agp_backend.h>
>> #include <linux/stop_machine.h>
>>
>> #include <asm/set_memory.h>
>> #include <asm/smp.h>
>>
>> #include <drm/i915_drm.h>
>> -#include <drm/intel-gtt.h>
>>
>> #include "gem/i915_gem_lmem.h"
>>
>> @@ -21,6 +19,7 @@
>> #include "i915_vgpu.h"
>>
>> #include "intel_gtt.h"
>> +#include "intel_gtt_support.h"
>> #include "gen8_ppgtt.h"
>>
>> static void i915_ggtt_color_adjust(const struct drm_mm_node *node,
>> @@ -98,7 +97,7 @@ int i915_ggtt_init_hw(struct drm_i915_private *i915)
>>  * Certain Gen5 chipsets require idling the GPU before
>>  * unmapping anything from the GTT when VT-d is enabled.
>>  */
>> -static bool needs_idle_maps(struct drm_i915_private *i915)
>> +bool needs_idle_maps(struct drm_i915_private *i915)
> 
> why didn't you move this function together? It's only used by
> i915_gmch_probe()
> 
> If it was something generic that needed to be exported, you'd need to
> rename it to respect the namespace.
> 
> but here I think you can just move it to the new file.
> 
>> {
>>     /*
>>      * Query intel_iommu to see if we need the workaround. Presumably 
>> that
>> @@ -229,11 +228,6 @@ static void guc_ggtt_invalidate(struct i915_ggtt 
>> *ggtt)
>>         intel_uncore_write_fw(uncore, GEN8_GTCR, GEN8_GTCR_INVALIDATE);
>> }
>>
>> -static void gmch_ggtt_invalidate(struct i915_ggtt *ggtt)
>> -{
>> -    intel_gtt_chipset_flush();
>> -}
>> -
>> u64 gen8_ggtt_pte_encode(dma_addr_t addr,
>>              enum i915_cache_level level,
>>              u32 flags)
>> @@ -467,37 +461,7 @@ static void gen6_ggtt_clear_range(struct 
>> i915_address_space *vm,
>>         iowrite32(scratch_pte, &gtt_base[i]);
>> }
>>
>> -static void i915_ggtt_insert_page(struct i915_address_space *vm,
>> -                  dma_addr_t addr,
>> -                  u64 offset,
>> -                  enum i915_cache_level cache_level,
>> -                  u32 unused)
>> -{
>> -    unsigned int flags = (cache_level == I915_CACHE_NONE) ?
>> -        AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
>> -
>> -    intel_gtt_insert_page(addr, offset >> PAGE_SHIFT, flags);
>> -}
>> -
>> -static void i915_ggtt_insert_entries(struct i915_address_space *vm,
>> -                     struct i915_vma_resource *vma_res,
>> -                     enum i915_cache_level cache_level,
>> -                     u32 unused)
>> -{
>> -    unsigned int flags = (cache_level == I915_CACHE_NONE) ?
>> -        AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
>> -
>> -    intel_gtt_insert_sg_entries(vma_res->bi.pages, vma_res->start >> 
>> PAGE_SHIFT,
>> -                    flags);
>> -}
>> -
>> -static void i915_ggtt_clear_range(struct i915_address_space *vm,
>> -                  u64 start, u64 length)
>> -{
>> -    intel_gtt_clear_range(start >> PAGE_SHIFT, length >> PAGE_SHIFT);
>> -}
>> -
>> -static void ggtt_bind_vma(struct i915_address_space *vm,
>> +void ggtt_bind_vma(struct i915_address_space *vm,
>>               struct i915_vm_pt_stash *stash,
>>               struct i915_vma_resource *vma_res,
>>               enum i915_cache_level cache_level,
>> @@ -521,7 +485,7 @@ static void ggtt_bind_vma(struct 
>> i915_address_space *vm,
>>     vma_res->page_sizes_gtt = I915_GTT_PAGE_SIZE;
>> }
>>
>> -static void ggtt_unbind_vma(struct i915_address_space *vm,
>> +void ggtt_unbind_vma(struct i915_address_space *vm,
>>                 struct i915_vma_resource *vma_res)
>> {
>>     vm->clear_range(vm, vma_res->start, vma_res->vma_size);
>> @@ -1149,54 +1113,6 @@ static int gen6_gmch_probe(struct i915_ggtt *ggtt)
>>     return ggtt_probe_common(ggtt, size);
>> }
>>
>> -static void i915_gmch_remove(struct i915_address_space *vm)
>> -{
>> -    intel_gmch_remove();
>> -}
>> -
>> -static int i915_gmch_probe(struct i915_ggtt *ggtt)
>> -{
>> -    struct drm_i915_private *i915 = ggtt->vm.i915;
>> -    phys_addr_t gmadr_base;
>> -    int ret;
>> -
>> -    ret = intel_gmch_probe(i915->bridge_dev, 
>> to_pci_dev(i915->drm.dev), NULL);
>> -    if (!ret) {
>> -        drm_err(&i915->drm, "failed to set up gmch\n");
>> -        return -EIO;
>> -    }
>> -
>> -    intel_gtt_get(&ggtt->vm.total, &gmadr_base, &ggtt->mappable_end);
>> -
>> -    ggtt->gmadr =
>> -        (struct resource)DEFINE_RES_MEM(gmadr_base, ggtt->mappable_end);
>> -
>> -    ggtt->vm.alloc_pt_dma = alloc_pt_dma;
>> -    ggtt->vm.alloc_scratch_dma = alloc_pt_dma;
>> -
>> -    if (needs_idle_maps(i915)) {
>> -        drm_notice(&i915->drm,
>> -               "Flushing DMA requests before IOMMU unmaps; 
>> performance may be degraded\n");
>> -        ggtt->do_idle_maps = true;
>> -    }
>> -
>> -    ggtt->vm.insert_page = i915_ggtt_insert_page;
>> -    ggtt->vm.insert_entries = i915_ggtt_insert_entries;
>> -    ggtt->vm.clear_range = i915_ggtt_clear_range;
>> -    ggtt->vm.cleanup = i915_gmch_remove;
>> -
>> -    ggtt->invalidate = gmch_ggtt_invalidate;
>> -
>> -    ggtt->vm.vma_ops.bind_vma    = ggtt_bind_vma;
>> -    ggtt->vm.vma_ops.unbind_vma  = ggtt_unbind_vma;
>> -
>> -    if (unlikely(ggtt->do_idle_maps))
>> -        drm_notice(&i915->drm,
>> -               "Applying Ironlake quirks for intel_iommu\n");
>> -
>> -    return 0;
>> -}
>> -
>> static int ggtt_probe_hw(struct i915_ggtt *ggtt, struct intel_gt *gt)
>> {
>>     struct drm_i915_private *i915 = gt->i915;
>> @@ -1266,10 +1182,7 @@ int i915_ggtt_probe_hw(struct drm_i915_private 
>> *i915)
>>
>> int i915_ggtt_enable_hw(struct drm_i915_private *i915)
>> {
>> -    if (GRAPHICS_VER(i915) < 6 && !intel_enable_gtt())
>> -        return -EIO;
>> -
>> -    return 0;
>> +    return i915_gtt_support_enable_hw(i915);
>> }
>>
>> void i915_ggtt_enable_guc(struct i915_ggtt *ggtt)
>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c 
>> b/drivers/gpu/drm/i915/gt/intel_gt.c
>> index 57ca1e6b6203..abdf8dc8ddf7 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
>> @@ -4,7 +4,6 @@
>>  */
>>
>> #include <drm/drm_managed.h>
>> -#include <drm/intel-gtt.h>
>>
>> #include "gem/i915_gem_internal.h"
>> #include "gem/i915_gem_lmem.h"
>> @@ -20,6 +19,7 @@
>> #include "intel_gt_pm.h"
>> #include "intel_gt_regs.h"
>> #include "intel_gt_requests.h"
>> +#include "intel_gtt_support.h"
>> #include "intel_migrate.h"
>> #include "intel_mocs.h"
>> #include "intel_pm.h"
>> @@ -443,9 +443,7 @@ void intel_gt_flush_ggtt_writes(struct intel_gt *gt)
>>
>> void intel_gt_chipset_flush(struct intel_gt *gt)
>> {
>> -    wmb();
>> -    if (GRAPHICS_VER(gt->i915) < 6)
>> -        intel_gtt_chipset_flush();
>> +    intel_gtt_support_chipset_flush(gt);
> 
> humn... 2 things here:
> 
> 1) intel_gtt_support_* may not be a good name. Here it seems the
> function would return a boolean saying if chipset flush is supported.
> 
> Also, all the functions in intel_gtt_support_* are actually about
> support the i915 graphics card (not to be confused is i915, the name of
> the module). intel_gtt_* clashes with the other module. So, looking at
> the calls I'd actually call these e.g. gen5_gtt_chipset_flush()
> 
> This would follow what is done in other headers/sources like
> gen*_renderstate.*, gen*_ppgtt.*, etc
> 
> Then this function would become like:
> 
> void intel_gt_chipset_flush(struct intel_gt *gt)
> {
>      wmb();
>      if (GRAPHICS_VER(gt->i915) <= 5)
>          gen5_gtt_chipset_flush();
> }
> 
> So we split what is to be done for every gpu (the wmb()) from what is to
> be done for the older gens.
> 
> 
> What do you think? Jani / Matt?

And on Arm gen5_gtt_chipset_flush is a no-op stub - sounds good to me, 
exactly the concept we already talked about.

Also as discussed before, gmch related functions like i915_gmch_probe 
(and all that cascade in the call chain and remain static) should be 
moved to a file named intel_gt_gmch.[hc], not "support". Functions which 
are shared between gens can be exported from intel_gt.[hc] like I think 
this patch does for some.

But don't export with no prefix like for instance ggtt_bind_vma. Add 
intel_ there. Or needs_idle_maps should become i915_... is needs to be 
exported. (I haven't looked into details.)

Regards,

Tvrtko

>>
>> void intel_gt_driver_register(struct intel_gt *gt)
>> diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h 
>> b/drivers/gpu/drm/i915/gt/intel_gtt.h
>> index 4529b5e9f6e6..fd1dea85bde4 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_gtt.h
>> +++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
>> @@ -547,6 +547,14 @@ i915_page_dir_dma_addr(const struct i915_ppgtt 
>> *ppgtt, const unsigned int n)
>> void ppgtt_init(struct i915_ppgtt *ppgtt, struct intel_gt *gt,
>>         unsigned long lmem_pt_obj_flags);
>>
>> +void ggtt_bind_vma(struct i915_address_space *vm,
>> +              struct i915_vm_pt_stash *stash,
>> +              struct i915_vma_resource *vma_res,
>> +              enum i915_cache_level cache_level,
>> +              u32 flags);
>> +void ggtt_unbind_vma(struct i915_address_space *vm,
>> +                struct i915_vma_resource *vma_res);
>> +
>> int i915_ggtt_probe_hw(struct drm_i915_private *i915);
>> int i915_ggtt_init_hw(struct drm_i915_private *i915);
>> int i915_ggtt_enable_hw(struct drm_i915_private *i915);
>> @@ -654,4 +662,6 @@ static inline struct sgt_dma {
>>     return (struct sgt_dma){ sg, addr, addr + sg_dma_len(sg) };
>> }
>>
>> +bool needs_idle_maps(struct drm_i915_private *i915);
>> +
>> #endif
>> diff --git a/drivers/gpu/drm/i915/gt/intel_gtt_support.c 
>> b/drivers/gpu/drm/i915/gt/intel_gtt_support.c
>> new file mode 100644
>> index 000000000000..d6d22b1a9520
>> --- /dev/null
>> +++ b/drivers/gpu/drm/i915/gt/intel_gtt_support.c
>> @@ -0,0 +1,113 @@
>> +// SPDX-License-Identifier: MIT
>> +/*
>> + * Copyright © 2022 Intel Corporation
>> + */
>> +
>> +#include <drm/intel-gtt.h>
>> +
>> +#include <linux/agp_backend.h>
>> +
>> +#include "i915_drv.h"
>> +#include "intel_gtt_support.h"
>> +#include "intel_gt.h"
>> +
>> +/* Wrapper for intel_gt_chipset_flush() */
>> +void intel_gtt_support_chipset_flush(struct intel_gt *gt)
>> +{
>> +    wmb();
>> +    if (GRAPHICS_VER(gt->i915) < 6)
>> +        intel_gtt_chipset_flush();
>> +}
>> +
>> +static void gmch_ggtt_invalidate(struct i915_ggtt *ggtt)
>> +{
>> +    intel_gtt_chipset_flush();
>> +}
>> +
>> +static void i915_ggtt_insert_page(struct i915_address_space *vm,
>> +                  dma_addr_t addr,
>> +                  u64 offset,
>> +                  enum i915_cache_level cache_level,
>> +                  u32 unused)
>> +{
>> +    unsigned int flags = (cache_level == I915_CACHE_NONE) ?
>> +        AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
>> +
>> +    intel_gtt_insert_page(addr, offset >> PAGE_SHIFT, flags);
>> +}
>> +
>> +static void i915_ggtt_insert_entries(struct i915_address_space *vm,
>> +                     struct i915_vma_resource *vma_res,
>> +                     enum i915_cache_level cache_level,
>> +                     u32 unused)
>> +{
>> +    unsigned int flags = (cache_level == I915_CACHE_NONE) ?
>> +        AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
>> +
>> +    intel_gtt_insert_sg_entries(vma_res->bi.pages, vma_res->start >> 
>> PAGE_SHIFT,
>> +                    flags);
>> +}
>> +
>> +static void i915_ggtt_clear_range(struct i915_address_space *vm,
>> +                     u64 start, u64 length)
>> +{
>> +    intel_gtt_clear_range(start >> PAGE_SHIFT, length >> PAGE_SHIFT);
>> +}
>> +
>> +static void i915_gmch_remove(struct i915_address_space *vm)
>> +{
>> +    intel_gmch_remove();
>> +}
>> +
>> +/* Original i915_gmch_probe() behavior for x86 */
>> +int i915_gmch_probe(struct i915_ggtt *ggtt)
>> +{
>> +    struct drm_i915_private *i915 = ggtt->vm.i915;
>> +    phys_addr_t gmadr_base;
>> +    int ret;
>> +
>> +    ret = intel_gmch_probe(i915->bridge_dev, 
>> to_pci_dev(i915->drm.dev), NULL);
>> +    if (!ret) {
>> +        drm_err(&i915->drm, "failed to set up gmch\n");
>> +        return -EIO;
>> +    }
>> +
>> +    intel_gtt_get(&ggtt->vm.total, &gmadr_base, &ggtt->mappable_end);
>> +
>> +    ggtt->gmadr =
>> +        (struct resource)DEFINE_RES_MEM(gmadr_base, ggtt->mappable_end);
>> +
>> +    ggtt->vm.alloc_pt_dma = alloc_pt_dma;
>> +    ggtt->vm.alloc_scratch_dma = alloc_pt_dma;
>> +
>> +    if (needs_idle_maps(i915)) {
>> +        drm_notice(&i915->drm,
>> +               "Flushing DMA requests before IOMMU unmaps; 
>> performance may be degraded\n");
>> +        ggtt->do_idle_maps = true;
>> +    }
>> +
>> +    ggtt->vm.insert_page = i915_ggtt_insert_page;
>> +    ggtt->vm.insert_entries = i915_ggtt_insert_entries;
>> +    ggtt->vm.clear_range = i915_ggtt_clear_range;
>> +    ggtt->vm.cleanup = i915_gmch_remove;
>> +
>> +    ggtt->invalidate = gmch_ggtt_invalidate;
>> +
>> +    ggtt->vm.vma_ops.bind_vma    = ggtt_bind_vma;
>> +    ggtt->vm.vma_ops.unbind_vma  = ggtt_unbind_vma;
>> +
>> +    if (unlikely(ggtt->do_idle_maps))
>> +        drm_notice(&i915->drm,
>> +               "Applying Ironlake quirks for intel_iommu\n");
>> +
>> +    return 0;
>> +}
>> +
>> +/* Wrapper for i915_ggtt_enable_hw() */
>> +int i915_gtt_support_enable_hw(struct drm_i915_private *i915)
>> +{
>> +    if (GRAPHICS_VER(i915) < 6 && !intel_enable_gtt())
>> +        return -EIO;
>> +
>> +    return 0;
>> +}
>> diff --git a/drivers/gpu/drm/i915/gt/intel_gtt_support.h 
>> b/drivers/gpu/drm/i915/gt/intel_gtt_support.h
>> new file mode 100644
>> index 000000000000..2ebb0dd66ad7
>> --- /dev/null
>> +++ b/drivers/gpu/drm/i915/gt/intel_gtt_support.h
>> @@ -0,0 +1,39 @@
>> +/* SPDX-License-Identifier: MIT */
>> +/*
>> + * Copyright © 2022 Intel Corporation
>> + */
>> +
>> +#ifndef __INTEL_GTT_SUPPORT_H__
>> +#define __INTEL_GTT_SUPPORT_H__
>> +
>> +#include "intel_gtt.h"
>> +
>> +/* For x86 platforms */
>> +#if IS_ENABLED(CONFIG_X86)
>> +/* Wrapper for intel_gt_chipset_flush() */
>> +void intel_gtt_support_chipset_flush(struct intel_gt *gt);
>> +/* Original i915_gmch_probe() behavior */
>> +int i915_gmch_probe(struct i915_ggtt *ggtt);
>> +/* Wrapper for i915_ggtt_enable_hw() */
>> +int i915_gtt_support_enable_hw(struct drm_i915_private *i915);
>> +
> 
> 
> we are trying to standardize on:
> 
> this_is_a_namespace.c / this_is_a_namespace.h
> 
> and the functions exported are:
> 
> this_is_a_namespace_*
> 
> Here you have 3 functions, all with different prefixes:
> 
> intel_gtt_support_
> i915_gmch_
> i915_ggtt_
> 
> we need to rename the functions we export. If people think my suggestion
> above with gen5_gtt_* is a good one, then this would be the namespace
> for all of them
> 
> I think we are now much closer to a version to be merged.
> 
> thanks,
> Lucas De Marchi
> 
>> +/* Stubs for non-x86 platforms */
>> +#else
>> +static inline void intel_gtt_support_chipset_flush(struct intel_gt *gt)
>> +{
>> +    return;
>> +}
>> +static inline int i915_gmch_probe(struct i915_ggtt *ggtt)
>> +{
>> +    /* We shouldn't detect a device in this case, return fail */
>> +    return -1;
>> +}
>> +
>> +static inline int i915_gtt_support_enable_hw(struct drm_i915_private 
>> *i915)
>> +{
>> +    /* No HW should be enabled for this case, return fail */
>> +    return -1;
>> +}
>> +#endif
>> +
>> +#endif /* __INTEL_GTT_SUPPORT_H__ */
>> -- 
>> 2.25.1
>>

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Splitting intel-gtt calls for non-x86 platforms

[Patchwork]

== Series Details ==

Series: Splitting intel-gtt calls for non-x86 platforms
URL   : https://patchwork.freedesktop.org/series/101552/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
71b8a3999b05 drm/i915: Require INTEL_GTT to depend on X86
6fb28942812c drm/i915/gt: Split intel-gtt functions by arch
-:112: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#112: FILE: drivers/gpu/drm/i915/gt/intel_ggtt.c:465:
+void ggtt_bind_vma(struct i915_address_space *vm,
 			  struct i915_vm_pt_stash *stash,

-:121: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#121: FILE: drivers/gpu/drm/i915/gt/intel_ggtt.c:489:
+void ggtt_unbind_vma(struct i915_address_space *vm,
 			    struct i915_vma_resource *vma_res)

-:231: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#231: FILE: drivers/gpu/drm/i915/gt/intel_gtt.h:551:
+void ggtt_bind_vma(struct i915_address_space *vm,
+			  struct i915_vm_pt_stash *stash,

-:236: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#236: FILE: drivers/gpu/drm/i915/gt/intel_gtt.h:556:
+void ggtt_unbind_vma(struct i915_address_space *vm,
+			    struct i915_vma_resource *vma_res);

-:249: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#249: 
new file mode 100644

-:270: WARNING:MEMORY_BARRIER: memory barrier without comment
#270: FILE: drivers/gpu/drm/i915/gt/intel_gtt_support.c:17:
+	wmb();

-:305: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#305: FILE: drivers/gpu/drm/i915/gt/intel_gtt_support.c:52:
+static void i915_ggtt_clear_range(struct i915_address_space *vm,
+					 u64 start, u64 length)

-:397: WARNING:RETURN_VOID: void function return statements are not generally useful
#397: FILE: drivers/gpu/drm/i915/gt/intel_gtt_support.h:25:
+	return;
+}

-:398: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations
#398: FILE: drivers/gpu/drm/i915/gt/intel_gtt_support.h:26:
+}
+static inline int i915_gmch_probe(struct i915_ggtt *ggtt)

total: 0 errors, 3 warnings, 6 checks, 355 lines checked

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Splitting intel-gtt calls for non-x86 platforms

[Patchwork]

== Series Details ==

Series: Splitting intel-gtt calls for non-x86 platforms
URL   : https://patchwork.freedesktop.org/series/101552/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✓ Fi.CI.BAT: success for Splitting intel-gtt calls for non-x86 platforms

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 3444 bytes --]

== Series Details ==

Series: Splitting intel-gtt calls for non-x86 platforms
URL   : https://patchwork.freedesktop.org/series/101552/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11385 -> Patchwork_22618
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/index.html

Participating hosts (46 -> 38)
------------------------------

  Missing    (8): fi-bxt-dsi fi-bdw-5557u shard-tglu bat-adlm-1 fi-bsw-cyan fi-pnv-d510 shard-rkl fi-bdw-samus 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_22618:

### IGT changes ###

#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_selftest@live@gt_lrc:
    - {bat-adlp-6}:       [PASS][1] -> [INCOMPLETE][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11385/bat-adlp-6/igt@i915_selftest@live@gt_lrc.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/bat-adlp-6/igt@i915_selftest@live@gt_lrc.html

  
Known issues
------------

  Here are the changes found in Patchwork_22618 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_selftest@live@gt_heartbeat:
    - fi-kbl-x1275:       [PASS][3] -> [DMESG-FAIL][4] ([i915#5334])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11385/fi-kbl-x1275/igt@i915_selftest@live@gt_heartbeat.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/fi-kbl-x1275/igt@i915_selftest@live@gt_heartbeat.html

  * igt@i915_selftest@live@hangcheck:
    - fi-snb-2600:        [PASS][5] -> [INCOMPLETE][6] ([i915#3921])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11385/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/fi-snb-2600/igt@i915_selftest@live@hangcheck.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
  [i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#5153]: https://gitlab.freedesktop.org/drm/intel/issues/5153
  [i915#5270]: https://gitlab.freedesktop.org/drm/intel/issues/5270
  [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
  [i915#5339]: https://gitlab.freedesktop.org/drm/intel/issues/5339
  [i915#5342]: https://gitlab.freedesktop.org/drm/intel/issues/5342
  [i915#5356]: https://gitlab.freedesktop.org/drm/intel/issues/5356


Build changes
-------------

  * Linux: CI_DRM_11385 -> Patchwork_22618

  CI-20190529: 20190529
  CI_DRM_11385: 3babe046f5f5544ec772cd443f9d5ca24e342348 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6386: 0fcd59ad25b2960c0b654f90dfe4dd9e7c7b874d @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_22618: 6fb28942812c08593386bbfaf5e15c47bc4eddfb @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

6fb28942812c drm/i915/gt: Split intel-gtt functions by arch
71b8a3999b05 drm/i915: Require INTEL_GTT to depend on X86

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/index.html

[-- Attachment #2: Type: text/html, Size: 3647 bytes --]

[Intel-gfx] ✓ Fi.CI.IGT: success for Splitting intel-gtt calls for non-x86 platforms

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 30271 bytes --]

== Series Details ==

Series: Splitting intel-gtt calls for non-x86 platforms
URL   : https://patchwork.freedesktop.org/series/101552/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11385_full -> Patchwork_22618_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (12 -> 12)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in Patchwork_22618_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_eio@kms:
    - shard-tglb:         [PASS][1] -> [FAIL][2] ([i915#232])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11385/shard-tglb8/igt@gem_eio@kms.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-tglb2/igt@gem_eio@kms.html

  * igt@gem_exec_balancer@parallel-balancer:
    - shard-iclb:         [PASS][3] -> [SKIP][4] ([i915#4525])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11385/shard-iclb1/igt@gem_exec_balancer@parallel-balancer.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-iclb3/igt@gem_exec_balancer@parallel-balancer.html

  * igt@gem_exec_balancer@parallel-contexts:
    - shard-kbl:          NOTRUN -> [DMESG-WARN][5] ([i915#5076])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-kbl7/igt@gem_exec_balancer@parallel-contexts.html

  * igt@gem_exec_fair@basic-none-share@rcs0:
    - shard-iclb:         [PASS][6] -> [FAIL][7] ([i915#2842])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11385/shard-iclb7/igt@gem_exec_fair@basic-none-share@rcs0.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-iclb7/igt@gem_exec_fair@basic-none-share@rcs0.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
    - shard-glk:          [PASS][8] -> [FAIL][9] ([i915#2842])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11385/shard-glk5/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-glk8/igt@gem_exec_fair@basic-pace-share@rcs0.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
    - shard-glk:          NOTRUN -> [FAIL][10] ([i915#2842])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-glk4/igt@gem_exec_fair@basic-throttle@rcs0.html

  * igt@gem_exec_params@no-blt:
    - shard-tglb:         NOTRUN -> [SKIP][11] ([fdo#109283])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-tglb3/igt@gem_exec_params@no-blt.html

  * igt@gem_exec_params@no-vebox:
    - shard-skl:          NOTRUN -> [SKIP][12] ([fdo#109271]) +168 similar issues
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-skl10/igt@gem_exec_params@no-vebox.html

  * igt@gem_exec_whisper@basic-queues-forked:
    - shard-glk:          NOTRUN -> [DMESG-WARN][13] ([i915#118])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-glk4/igt@gem_exec_whisper@basic-queues-forked.html

  * igt@gem_lmem_swapping@heavy-verify-random:
    - shard-skl:          NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#4613]) +2 similar issues
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-skl1/igt@gem_lmem_swapping@heavy-verify-random.html

  * igt@gem_lmem_swapping@random:
    - shard-kbl:          NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#4613]) +1 similar issue
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-kbl7/igt@gem_lmem_swapping@random.html

  * igt@kms_async_flips@crc:
    - shard-skl:          NOTRUN -> [FAIL][16] ([i915#4272])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-skl10/igt@kms_async_flips@crc.html

  * igt@kms_big_fb@linear-8bpp-rotate-90:
    - shard-iclb:         NOTRUN -> [SKIP][17] ([fdo#110725] / [fdo#111614])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-iclb7/igt@kms_big_fb@linear-8bpp-rotate-90.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
    - shard-skl:          NOTRUN -> [FAIL][18] ([i915#3743])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-skl4/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip:
    - shard-apl:          NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#3777])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-apl3/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip:
    - shard-kbl:          NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#3777]) +1 similar issue
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-kbl4/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
    - shard-skl:          NOTRUN -> [FAIL][21] ([i915#3763])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-skl10/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip:
    - shard-skl:          NOTRUN -> [SKIP][22] ([fdo#109271] / [i915#3777])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-skl1/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip.html

  * igt@kms_big_fb@yf-tiled-64bpp-rotate-270:
    - shard-iclb:         NOTRUN -> [SKIP][23] ([fdo#110723])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-iclb7/igt@kms_big_fb@yf-tiled-64bpp-rotate-270.html

  * igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_gen12_mc_ccs:
    - shard-glk:          NOTRUN -> [SKIP][24] ([fdo#109271] / [i915#3886]) +1 similar issue
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-glk4/igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-a-crc-primary-basic-y_tiled_gen12_rc_ccs_cc:
    - shard-apl:          NOTRUN -> [SKIP][25] ([fdo#109271] / [i915#3886])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-apl3/igt@kms_ccs@pipe-a-crc-primary-basic-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc:
    - shard-skl:          NOTRUN -> [SKIP][26] ([fdo#109271] / [i915#3886]) +7 similar issues
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-skl10/igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-d-crc-sprite-planes-basic-yf_tiled_ccs:
    - shard-glk:          NOTRUN -> [SKIP][27] ([fdo#109271]) +25 similar issues
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-glk4/igt@kms_ccs@pipe-d-crc-sprite-planes-basic-yf_tiled_ccs.html

  * igt@kms_cdclk@mode-transition:
    - shard-apl:          NOTRUN -> [SKIP][28] ([fdo#109271]) +8 similar issues
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-apl3/igt@kms_cdclk@mode-transition.html

  * igt@kms_chamelium@dp-hpd-with-enabled-mode:
    - shard-glk:          NOTRUN -> [SKIP][29] ([fdo#109271] / [fdo#111827]) +4 similar issues
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-glk4/igt@kms_chamelium@dp-hpd-with-enabled-mode.html

  * igt@kms_color_chamelium@pipe-a-ctm-negative:
    - shard-kbl:          NOTRUN -> [SKIP][30] ([fdo#109271] / [fdo#111827]) +2 similar issues
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-kbl4/igt@kms_color_chamelium@pipe-a-ctm-negative.html

  * igt@kms_color_chamelium@pipe-b-ctm-max:
    - shard-skl:          NOTRUN -> [SKIP][31] ([fdo#109271] / [fdo#111827]) +11 similar issues
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-skl4/igt@kms_color_chamelium@pipe-b-ctm-max.html
    - shard-tglb:         NOTRUN -> [SKIP][32] ([fdo#109284] / [fdo#111827])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-tglb3/igt@kms_color_chamelium@pipe-b-ctm-max.html

  * igt@kms_color_chamelium@pipe-d-ctm-negative:
    - shard-iclb:         NOTRUN -> [SKIP][33] ([fdo#109278] / [fdo#109284] / [fdo#111827])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-iclb7/igt@kms_color_chamelium@pipe-d-ctm-negative.html

  * igt@kms_cursor_crc@pipe-a-cursor-32x10-onscreen:
    - shard-iclb:         NOTRUN -> [SKIP][34] ([fdo#109278]) +1 similar issue
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-iclb7/igt@kms_cursor_crc@pipe-a-cursor-32x10-onscreen.html

  * igt@kms_cursor_crc@pipe-a-cursor-512x170-sliding:
    - shard-tglb:         NOTRUN -> [SKIP][35] ([fdo#109279] / [i915#3359])
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-tglb3/igt@kms_cursor_crc@pipe-a-cursor-512x170-sliding.html

  * igt@kms_cursor_crc@pipe-a-cursor-512x512-offscreen:
    - shard-iclb:         NOTRUN -> [SKIP][36] ([fdo#109278] / [fdo#109279])
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-iclb7/igt@kms_cursor_crc@pipe-a-cursor-512x512-offscreen.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
    - shard-iclb:         [PASS][37] -> [FAIL][38] ([i915#2346])
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11385/shard-iclb4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-iclb7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html

  * igt@kms_flip@flip-vs-suspend-interruptible@c-dp1:
    - shard-apl:          [PASS][39] -> [DMESG-WARN][40] ([i915#180]) +2 similar issues
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11385/shard-apl7/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html

  * igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1:
    - shard-skl:          [PASS][41] -> [FAIL][42] ([i915#2122]) +2 similar issues
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11385/shard-skl1/igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-skl8/igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling:
    - shard-iclb:         [PASS][43] -> [SKIP][44] ([i915#3701])
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11385/shard-iclb5/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-pgflip-blt:
    - shard-iclb:         NOTRUN -> [SKIP][45] ([fdo#109280]) +2 similar issues
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-iclb7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-pgflip-blt.html

  * igt@kms_pipe_crc_basic@hang-read-crc-pipe-d:
    - shard-kbl:          NOTRUN -> [SKIP][46] ([fdo#109271] / [i915#533])
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-kbl4/igt@kms_pipe_crc_basic@hang-read-crc-pipe-d.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
    - shard-kbl:          [PASS][47] -> [DMESG-WARN][48] ([i915#180]) +1 similar issue
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11385/shard-kbl1/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-kbl6/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html

  * igt@kms_plane_alpha_blend@pipe-c-alpha-basic:
    - shard-glk:          NOTRUN -> [FAIL][49] ([fdo#108145] / [i915#265])
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-glk4/igt@kms_plane_alpha_blend@pipe-c-alpha-basic.html

  * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
    - shard-skl:          NOTRUN -> [FAIL][50] ([fdo#108145] / [i915#265]) +2 similar issues
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-skl4/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html

  * igt@kms_plane_scaling@downscale-with-rotation-factor-0-5@pipe-a-dp-1-downscale-with-rotation:
    - shard-kbl:          NOTRUN -> [SKIP][51] ([fdo#109271]) +42 similar issues
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-kbl7/igt@kms_plane_scaling@downscale-with-rotation-factor-0-5@pipe-a-dp-1-downscale-with-rotation.html

  * igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-b-edp-1-scaler-with-clipping-clamping:
    - shard-iclb:         [PASS][52] -> [SKIP][53] ([i915#5176]) +1 similar issue
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11385/shard-iclb8/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-b-edp-1-scaler-with-clipping-clamping.html
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-iclb3/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-b-edp-1-scaler-with-clipping-clamping.html

  * igt@kms_psr2_sf@plane-move-sf-dmg-area:
    - shard-skl:          NOTRUN -> [SKIP][54] ([fdo#109271] / [i915#658]) +3 similar issues
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-skl4/igt@kms_psr2_sf@plane-move-sf-dmg-area.html

  * igt@kms_psr@psr2_cursor_mmap_cpu:
    - shard-iclb:         [PASS][55] -> [SKIP][56] ([fdo#109441]) +1 similar issue
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11385/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-iclb1/igt@kms_psr@psr2_cursor_mmap_cpu.html

  * igt@kms_psr@psr2_cursor_plane_onoff:
    - shard-iclb:         NOTRUN -> [SKIP][57] ([fdo#109441])
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-iclb7/igt@kms_psr@psr2_cursor_plane_onoff.html

  * igt@kms_vblank@pipe-d-wait-idle:
    - shard-skl:          NOTRUN -> [SKIP][58] ([fdo#109271] / [i915#533]) +1 similar issue
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-skl4/igt@kms_vblank@pipe-d-wait-idle.html

  * igt@syncobj_timeline@transfer-timeline-point:
    - shard-kbl:          NOTRUN -> [DMESG-FAIL][59] ([i915#5098])
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-kbl1/igt@syncobj_timeline@transfer-timeline-point.html

  * igt@sysfs_clients@fair-7:
    - shard-skl:          NOTRUN -> [SKIP][60] ([fdo#109271] / [i915#2994]) +1 similar issue
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-skl10/igt@sysfs_clients@fair-7.html

  * igt@sysfs_clients@split-50:
    - shard-kbl:          NOTRUN -> [SKIP][61] ([fdo#109271] / [i915#2994]) +1 similar issue
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-kbl4/igt@sysfs_clients@split-50.html

  
#### Possible fixes ####

  * igt@feature_discovery@psr2:
    - shard-iclb:         [SKIP][62] ([i915#658]) -> [PASS][63]
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11385/shard-iclb5/igt@feature_discovery@psr2.html
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-iclb2/igt@feature_discovery@psr2.html

  * igt@gem_eio@unwedge-stress:
    - {shard-tglu}:       [TIMEOUT][64] ([i915#3063] / [i915#3648]) -> [PASS][65]
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11385/shard-tglu-2/igt@gem_eio@unwedge-stress.html
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-tglu-5/igt@gem_eio@unwedge-stress.html

  * igt@gem_exec_fair@basic-none@vcs0:
    - shard-apl:          [FAIL][66] ([i915#2842]) -> [PASS][67]
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11385/shard-apl2/igt@gem_exec_fair@basic-none@vcs0.html
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-apl8/igt@gem_exec_fair@basic-none@vcs0.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
    - {shard-tglu}:       [FAIL][68] ([i915#2842]) -> [PASS][69]
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11385/shard-tglu-2/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-tglu-5/igt@gem_exec_fair@basic-pace-share@rcs0.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
    - shard-kbl:          [FAIL][70] ([i915#2842]) -> [PASS][71]
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11385/shard-kbl6/igt@gem_exec_fair@basic-pace-solo@rcs0.html
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-kbl4/igt@gem_exec_fair@basic-pace-solo@rcs0.html

  * igt@gem_exec_suspend@basic-s0@smem:
    - {shard-rkl}:        [INCOMPLETE][72] -> [PASS][73]
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11385/shard-rkl-5/igt@gem_exec_suspend@basic-s0@smem.html
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-rkl-6/igt@gem_exec_suspend@basic-s0@smem.html

  * igt@gen9_exec_parse@allowed-all:
    - shard-glk:          [DMESG-WARN][74] ([i915#1436] / [i915#716]) -> [PASS][75]
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11385/shard-glk7/igt@gen9_exec_parse@allowed-all.html
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-glk4/igt@gen9_exec_parse@allowed-all.html

  * igt@i915_pm_dc@dc6-psr:
    - {shard-rkl}:        [SKIP][76] ([i915#658]) -> [PASS][77]
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11385/shard-rkl-1/igt@i915_pm_dc@dc6-psr.html
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-rkl-6/igt@i915_pm_dc@dc6-psr.html

  * igt@i915_pm_rpm@modeset-lpsp-stress:
    - {shard-rkl}:        [SKIP][78] ([i915#1397]) -> [PASS][79]
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11385/shard-rkl-1/igt@i915_pm_rpm@modeset-lpsp-stress.html
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-rkl-6/igt@i915_pm_rpm@modeset-lpsp-stress.html

  * igt@i915_suspend@fence-restore-untiled:
    - shard-apl:          [DMESG-WARN][80] ([i915#180]) -> [PASS][81]
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11385/shard-apl4/igt@i915_suspend@fence-restore-untiled.html
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-apl3/igt@i915_suspend@fence-restore-untiled.html

  * igt@kms_color@pipe-a-legacy-gamma-reset:
    - {shard-rkl}:        [SKIP][82] ([i915#1849] / [i915#4070] / [i915#4098]) -> [PASS][83] +1 similar issue
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11385/shard-rkl-1/igt@kms_color@pipe-a-legacy-gamma-reset.html
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-rkl-6/igt@kms_color@pipe-a-legacy-gamma-reset.html

  * igt@kms_color@pipe-b-ctm-0-25:
    - {shard-rkl}:        [SKIP][84] ([i915#1149] / [i915#1849] / [i915#4070] / [i915#4098]) -> [PASS][85]
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11385/shard-rkl-1/igt@kms_color@pipe-b-ctm-0-25.html
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-rkl-6/igt@kms_color@pipe-b-ctm-0-25.html

  * igt@kms_cursor_crc@pipe-a-cursor-64x64-random:
    - {shard-rkl}:        [SKIP][86] ([fdo#112022] / [i915#4070]) -> [PASS][87] +2 similar issues
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11385/shard-rkl-1/igt@kms_cursor_crc@pipe-a-cursor-64x64-random.html
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-rkl-6/igt@kms_cursor_crc@pipe-a-cursor-64x64-random.html

  * igt@kms_cursor_crc@pipe-a-cursor-suspend:
    - shard-kbl:          [DMESG-WARN][88] ([i915#180]) -> [PASS][89] +1 similar issue
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11385/shard-kbl6/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-kbl7/igt@kms_cursor_crc@pipe-a-cursor-suspend.html

  * igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size:
    - {shard-rkl}:        [SKIP][90] ([fdo#111825] / [i915#4070]) -> [PASS][91] +2 similar issues
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11385/shard-rkl-5/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size.html
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-rkl-6/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@cursora-vs-flipa-atomic-transitions-varying-size:
    - {shard-rkl}:        ([SKIP][92], [SKIP][93]) ([fdo#111825] / [i915#4070]) -> [PASS][94]
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11385/shard-rkl-4/igt@kms_cursor_legacy@cursora-vs-flipa-atomic-transitions-varying-size.html
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11385/shard-rkl-1/igt@kms_cursor_legacy@cursora-vs-flipa-atomic-transitions-varying-size.html
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-rkl-6/igt@kms_cursor_legacy@cursora-vs-flipa-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@pipe-c-forked-move:
    - {shard-rkl}:        [SKIP][95] ([i915#4070]) -> [PASS][96]
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11385/shard-rkl-6/igt@kms_cursor_legacy@pipe-c-forked-move.html
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-rkl-5/igt@kms_cursor_legacy@pipe-c-forked-move.html

  * igt@kms_fbcon_fbt@fbc-suspend:
    - shard-kbl:          [INCOMPLETE][97] ([i915#180] / [i915#636]) -> [PASS][98]
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11385/shard-kbl6/igt@kms_fbcon_fbt@fbc-suspend.html
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-kbl1/igt@kms_fbcon_fbt@fbc-suspend.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling:
    - {shard-rkl}:        [INCOMPLETE][99] ([i915#3701]) -> [PASS][100]
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11385/shard-rkl-5/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling.html
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-rkl-6/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling.html

  * igt@kms_frontbuffer_tracking@fbcpsr-suspend:
    - {shard-rkl}:        [SKIP][101] ([i915#1849]) -> [PASS][102] +10 similar issues
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11385/shard-rkl-1/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html

  * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-blt:
    - {shard-rkl}:        ([SKIP][103], [SKIP][104]) ([i915#1849] / [i915#4098]) -> [PASS][105] +1 similar issue
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11385/shard-rkl-5/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-blt.html
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11385/shard-rkl-4/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-blt.html
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-blt.html

  * igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-b:
    - {shard-rkl}:        [SKIP][106] ([i915#1849] / [i915#4098]) -> [PASS][107] +1 similar issue
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11385/shard-rkl-1/igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-b.html
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-rkl-6/igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-b.html

  * igt@kms_plane@plane-position-hole-dpms@pipe-b-planes:
    - {shard-rkl}:        [SKIP][108] ([i915#3558]) -> [PASS][109] +1 similar issue
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11385/shard-rkl-1/igt@kms_plane@plane-position-hole-dpms@pipe-b-planes.html
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-rkl-6/igt@kms_plane@plane-position-hole-dpms@pipe-b-planes.html

  * igt@kms_psr@psr2_cursor_blt:
    - shard-iclb:         [SKIP][110] ([fdo#109441]) -> [PASS][111] +1 similar issue
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11385/shard-iclb5/igt@kms_psr@psr2_cursor_blt.html
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-iclb2/igt@kms_psr@psr2_cursor_blt.html

  * igt@kms_psr@sprite_mmap_cpu:
    - {shard-rkl}:        [SKIP][112] ([i915#1072]) -> [PASS][113] +1 similar issue
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11385/shard-rkl-5/igt@kms_psr@sprite_mmap_cpu.html
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-rkl-6/igt@kms_psr@sprite_mmap_cpu.html

  * igt@kms_universal_plane@universal-plane-pipe-b-functional:
    - {shard-rkl}:        [SKIP][114] ([i915#1845] / [i915#4070] / [i915#4098]) -> [PASS][115]
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11385/shard-rkl-5/igt@kms_universal_plane@universal-plane-pipe-b-functional.html
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-rkl-6/igt@kms_universal_plane@universal-plane-pipe-b-functional.html

  * igt@kms_vblank@pipe-a-ts-continuation-modeset:
    - {shard-rkl}:        [SKIP][116] ([i915#1845] / [i915#4098]) -> [PASS][117] +13 similar issues
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11385/shard-rkl-1/igt@kms_vblank@pipe-a-ts-continuation-modeset.html
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-rkl-6/igt@kms_vblank@pipe-a-ts-continuation-modeset.html

  
#### Warnings ####

  * igt@gem_exec_balancer@parallel:
    - shard-iclb:         [DMESG-WARN][118] ([i915#5076]) -> [SKIP][119] ([i915#4525])
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11385/shard-iclb4/igt@gem_exec_balancer@parallel.html
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-iclb7/igt@gem_exec_balancer@parallel.html

  * igt@gem_exec_balancer@parallel-ordering:
    - shard-iclb:         [SKIP][120] ([i915#4525]) -> [DMESG-FAIL][121] ([i915#5076])
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11385/shard-iclb6/igt@gem_exec_balancer@parallel-ordering.html
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-iclb2/igt@gem_exec_balancer@parallel-ordering.html

  * igt@gem_exec_balancer@parallel-out-fence:
    - shard-iclb:         [SKIP][122] ([i915#4525]) -> [DMESG-WARN][123] ([i915#5076]) +1 similar issue
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11385/shard-iclb3/igt@gem_exec_balancer@parallel-out-fence.html
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-iclb1/igt@gem_exec_balancer@parallel-out-fence.html

  * igt@i915_pm_dc@dc3co-vpb-simulation:
    - shard-iclb:         [SKIP][124] ([i915#658]) -> [SKIP][125] ([i915#588])
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11385/shard-iclb5/igt@i915_pm_dc@dc3co-vpb-simulation.html
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html

  * igt@i915_pm_rc6_residency@rc6-fence:
    - shard-iclb:         [WARN][126] ([i915#2684]) -> [WARN][127] ([i915#1804] / [i915#2684])
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11385/shard-iclb5/igt@i915_pm_rc6_residency@rc6-fence.html
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-iclb7/igt@i915_pm_rc6_residency@rc6-fence.html

  * igt@i915_pm_rc6_residency@rc6-idle:
    - shard-iclb:         [WARN][128] ([i915#1804] / [i915#2684]) -> [WARN][129] ([i915#2684])
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11385/shard-iclb7/igt@i915_pm_rc6_residency@rc6-idle.html
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-iclb5/igt@i915_pm_rc6_residency@rc6-idle.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1:
    - shard-skl:          [FAIL][130] ([i915#79]) -> [FAIL][131] ([i915#2122])
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11385/shard-skl8/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-wc:
    - shard-skl:          [SKIP][132] ([fdo#109271]) -> [SKIP][133] ([fdo#109271] / [i915#1888])
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11385/shard-skl10/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-wc.html
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-skl2/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-render:
    - shard-skl:          [SKIP][134] ([fdo#109271] / [i915#1888]) -> [SKIP][135] ([fdo#109271])
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11385/shard-skl10/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-render.html
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-skl8/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-render.html

  * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area:
    - shard-iclb:         [SKIP][136] ([fdo#111068] / [i915#658]) -> [SKIP][137] ([i915#2920])
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11385/shard-iclb4/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area.html
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area.html

  * igt@runner@aborted:
    - shard-kbl:          ([FAIL][138], [FAIL][139], [FAIL][140], [FAIL][141], [FAIL][142], [FAIL][143], [FAIL][144], [FAIL][145], [FAIL][146], [FAIL][147], [FAIL][148], [FAIL][149], [FAIL][150]) ([i915#180] / [i915#1814] / [i915#3002] / [i915#4312] / [i915#5257] / [i915#602] / [i915#92]) -> ([FAIL][151], [FAIL][152], [FAIL][153], [FAIL][154], [FAIL][155], [FAIL][156], [FAIL][157], [FAIL][158], [FAIL][159], [FAIL][160], [FAIL][161], [FAIL][162], [FAIL][163], [FAIL][164]) ([i915#180] / [i915#1814] / [i915#3002] / [i915#4312] / [i915#5257] / [i915#602])
   [138]: https://intel-gfx-ci.01.org/tree/dr

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22618/index.html

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