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From: Michael Cheng <michael.cheng@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: michael.cheng@intel.com, lucas.demarchi@intel.com,
	dri-devel@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v13 0/5] Use drm_clflush* instead of clflush
Date: Mon, 21 Mar 2022 15:38:14 -0700	[thread overview]
Message-ID: <20220321223819.72833-1-michael.cheng@intel.com> (raw)

This patch series re-work a few i915 functions to use drm_clflush_virt_range
instead of calling clflush or clflushopt directly. This will prevent errors
when building for non-x86 architectures.

v2: s/PAGE_SIZE/sizeof(value) for Re-work intel_write_status_page and added
more patches to convert additional clflush/clflushopt to use drm_clflush*.
(Michael Cheng)

v3: Drop invalidate_csb_entries and directly invoke drm_clflush_virt_ran

v4: Remove extra memory barriers

v5: s/cache_clflush_range/drm_clflush_virt_range

v6: Fix up "Drop invalidate_csb_entries" to use correct parameters. Also
added in arm64 support for drm_clflush_virt_range.

v7: Re-order patches, and use correct macro for dcache flush for arm64.

v8: Remove ifdef for asm/cacheflush.

v9: Rebased

v10: Replaced asm/cacheflush with linux/cacheflush

v11: Correctly get the sizeof certian addresses. Also rebased to the latest.

v12: Drop include of cacheflush.h and use caches_clean_inval_pou instead of
dcache_clean_inval_poc, since it is not exported for other modules to use.

v13: Drop arm64 implementation for drm_clflush_virt_range. This series will 
focus more on making i915 more architecture neutral by abstracting all clflush
and clflush opt to the drm layer. 

Michael Cheng (5):
  drm/i915/gt: Re-work intel_write_status_page
  drm/i915/gt: Drop invalidate_csb_entries
  drm/i915/gt: Re-work reset_csb
  drm/i915/: Re-work clflush_write32
  drm/i915/gt: replace cache_clflush_range

 .../gpu/drm/i915/gem/i915_gem_execbuffer.c    |  8 +++-----
 drivers/gpu/drm/i915/gt/gen8_ppgtt.c          | 12 +++++------
 drivers/gpu/drm/i915/gt/intel_engine.h        | 13 ++++--------
 .../drm/i915/gt/intel_execlists_submission.c  | 20 +++++++------------
 drivers/gpu/drm/i915/gt/intel_gtt.c           |  2 +-
 drivers/gpu/drm/i915/gt/intel_ppgtt.c         |  2 +-
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c |  2 +-
 7 files changed, 23 insertions(+), 36 deletions(-)

-- 
2.25.1


             reply	other threads:[~2022-03-21 22:38 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-03-21 22:38 Michael Cheng [this message]
2022-03-21 22:38 ` [Intel-gfx] [PATCH v13 1/5] drm/i915/gt: Re-work intel_write_status_page Michael Cheng
2022-03-21 22:38 ` [Intel-gfx] [PATCH v13 2/5] drm/i915/gt: Drop invalidate_csb_entries Michael Cheng
2022-03-21 22:38 ` [Intel-gfx] [PATCH v13 3/5] drm/i915/gt: Re-work reset_csb Michael Cheng
2022-03-21 22:38 ` [Intel-gfx] [PATCH v13 4/5] drm/i915/: Re-work clflush_write32 Michael Cheng
2022-03-21 22:38 ` [Intel-gfx] [PATCH v13 5/5] drm/i915/gt: replace cache_clflush_range Michael Cheng
2022-03-22  1:14 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Use drm_clflush* instead of clflush Patchwork
2022-03-22  1:18 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
2022-03-22  1:48 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-03-22 14:09 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2022-03-22 17:15   ` Matt Roper

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