From: Michael Cheng <michael.cheng@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: michael.cheng@intel.com, lucas.demarchi@intel.com,
dri-devel@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v13 4/5] drm/i915/: Re-work clflush_write32
Date: Mon, 21 Mar 2022 15:38:18 -0700 [thread overview]
Message-ID: <20220321223819.72833-5-michael.cheng@intel.com> (raw)
In-Reply-To: <20220321223819.72833-1-michael.cheng@intel.com>
Use drm_clflush_virt_range instead of clflushopt and remove the memory
barrier, since drm_clflush_virt_range takes care of that.
v2(Michael Cheng): Use sizeof(*addr) instead of sizeof(addr) to get the
actual size of the page. Thanks to Matt Roper for
pointing this out.
Signed-off-by: Michael Cheng <michael.cheng@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 8 +++-----
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 631bc268e7c8..42a49fd2f2ab 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -1334,10 +1334,8 @@ static void *reloc_vaddr(struct i915_vma *vma,
static void clflush_write32(u32 *addr, u32 value, unsigned int flushes)
{
if (unlikely(flushes & (CLFLUSH_BEFORE | CLFLUSH_AFTER))) {
- if (flushes & CLFLUSH_BEFORE) {
- clflushopt(addr);
- mb();
- }
+ if (flushes & CLFLUSH_BEFORE)
+ drm_clflush_virt_range(addr, sizeof(*addr));
*addr = value;
@@ -1349,7 +1347,7 @@ static void clflush_write32(u32 *addr, u32 value, unsigned int flushes)
* to ensure ordering of clflush wrt to the system.
*/
if (flushes & CLFLUSH_AFTER)
- clflushopt(addr);
+ drm_clflush_virt_range(addr, sizeof(*addr));
} else
*addr = value;
}
--
2.25.1
next prev parent reply other threads:[~2022-03-21 22:38 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-21 22:38 [Intel-gfx] [PATCH v13 0/5] Use drm_clflush* instead of clflush Michael Cheng
2022-03-21 22:38 ` [Intel-gfx] [PATCH v13 1/5] drm/i915/gt: Re-work intel_write_status_page Michael Cheng
2022-03-21 22:38 ` [Intel-gfx] [PATCH v13 2/5] drm/i915/gt: Drop invalidate_csb_entries Michael Cheng
2022-03-21 22:38 ` [Intel-gfx] [PATCH v13 3/5] drm/i915/gt: Re-work reset_csb Michael Cheng
2022-03-21 22:38 ` Michael Cheng [this message]
2022-03-21 22:38 ` [Intel-gfx] [PATCH v13 5/5] drm/i915/gt: replace cache_clflush_range Michael Cheng
2022-03-22 1:14 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Use drm_clflush* instead of clflush Patchwork
2022-03-22 1:18 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
2022-03-22 1:48 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-03-22 14:09 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2022-03-22 17:15 ` Matt Roper
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