From: Michael Cheng <michael.cheng@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: michael.cheng@intel.com, lucas.demarchi@intel.com,
dri-devel@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v13 2/5] drm/i915/gt: Drop invalidate_csb_entries
Date: Mon, 21 Mar 2022 15:38:16 -0700 [thread overview]
Message-ID: <20220321223819.72833-3-michael.cheng@intel.com> (raw)
In-Reply-To: <20220321223819.72833-1-michael.cheng@intel.com>
Drop invalidate_csb_entries and directly call drm_clflush_virt_range.
This allows for one less function call, and prevent complier errors when
building for non-x86 architectures.
v2(Michael Cheng): Drop invalidate_csb_entries function and directly
invoke drm_clflush_virt_range. Thanks to Tvrtko for the
sugguestion.
v3(Michael Cheng): Use correct parameters for drm_clflush_virt_range.
Thanks to Tvrtko for pointing this out.
v4(Michael Cheng): Simplify &execlists->csb_status[0] to
execlists->csb_status. Thanks to Matt Roper for the
suggestion.
Signed-off-by: Michael Cheng <michael.cheng@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
---
.../gpu/drm/i915/gt/intel_execlists_submission.c | 13 ++++---------
1 file changed, 4 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index e1470bb60f34..5f8cf4942f07 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -1651,12 +1651,6 @@ cancel_port_requests(struct intel_engine_execlists * const execlists,
return inactive;
}
-static void invalidate_csb_entries(const u64 *first, const u64 *last)
-{
- clflush((void *)first);
- clflush((void *)last);
-}
-
/*
* Starting with Gen12, the status has a new format:
*
@@ -2004,7 +1998,7 @@ process_csb(struct intel_engine_cs *engine, struct i915_request **inactive)
* the wash as hardware, working or not, will need to do the
* invalidation before.
*/
- invalidate_csb_entries(&buf[0], &buf[num_entries - 1]);
+ drm_clflush_virt_range(&buf[0], num_entries * sizeof(buf[0]));
/*
* We assume that any event reflects a change in context flow
@@ -2788,8 +2782,9 @@ static void reset_csb_pointers(struct intel_engine_cs *engine)
/* Check that the GPU does indeed update the CSB entries! */
memset(execlists->csb_status, -1, (reset_value + 1) * sizeof(u64));
- invalidate_csb_entries(&execlists->csb_status[0],
- &execlists->csb_status[reset_value]);
+ drm_clflush_virt_range(execlists->csb_status,
+ execlists->csb_size *
+ sizeof(execlists->csb_status));
/* Once more for luck and our trusty paranoia */
ENGINE_WRITE(engine, RING_CONTEXT_STATUS_PTR,
--
2.25.1
next prev parent reply other threads:[~2022-03-21 22:38 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-21 22:38 [Intel-gfx] [PATCH v13 0/5] Use drm_clflush* instead of clflush Michael Cheng
2022-03-21 22:38 ` [Intel-gfx] [PATCH v13 1/5] drm/i915/gt: Re-work intel_write_status_page Michael Cheng
2022-03-21 22:38 ` Michael Cheng [this message]
2022-03-21 22:38 ` [Intel-gfx] [PATCH v13 3/5] drm/i915/gt: Re-work reset_csb Michael Cheng
2022-03-21 22:38 ` [Intel-gfx] [PATCH v13 4/5] drm/i915/: Re-work clflush_write32 Michael Cheng
2022-03-21 22:38 ` [Intel-gfx] [PATCH v13 5/5] drm/i915/gt: replace cache_clflush_range Michael Cheng
2022-03-22 1:14 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Use drm_clflush* instead of clflush Patchwork
2022-03-22 1:18 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
2022-03-22 1:48 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-03-22 14:09 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2022-03-22 17:15 ` Matt Roper
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