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From: Matt Roper <matthew.d.roper@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v2 1/4] drm/i915/uapi: Add kerneldoc for engine class enum
Date: Wed, 27 Apr 2022 21:19:23 -0700	[thread overview]
Message-ID: <20220428041926.1483683-2-matthew.d.roper@intel.com> (raw)
In-Reply-To: <20220428041926.1483683-1-matthew.d.roper@intel.com>

We'll be adding a new type of engine soon.  Let's document the existing
engine classes first to help make it clear what each type of engine is
used for.

Cc: Andi Shyti <andi.shyti@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 include/uapi/drm/i915_drm.h | 53 ++++++++++++++++++++++++++++++++-----
 1 file changed, 47 insertions(+), 6 deletions(-)

diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 35ca528803fd..ec000fc6c879 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -154,21 +154,62 @@ enum i915_mocs_table_index {
 	I915_MOCS_CACHED,
 };
 
-/*
+/**
+ * enum drm_i915_gem_engine_class - uapi engine type enumeration
+ *
  * Different engines serve different roles, and there may be more than one
- * engine serving each role. enum drm_i915_gem_engine_class provides a
- * classification of the role of the engine, which may be used when requesting
- * operations to be performed on a certain subset of engines, or for providing
- * information about that group.
+ * engine serving each role.  This enum provides a classification of the role
+ * of the engine, which may be used when requesting operations to be performed
+ * on a certain subset of engines, or for providing information about that
+ * group.
  */
 enum drm_i915_gem_engine_class {
+	/**
+	 * @I915_ENGINE_CLASS_RENDER:
+	 *
+	 * Render engines support instructions used for 3D, Compute (GPGPU),
+	 * and programmable media workloads.  These instructions fetch data and
+	 * dispatch individual work items to threads that operate in parallel.
+	 * The threads run small programs (called "kernels" or "shaders") on
+	 * the GPU's execution units (EUs).
+	 */
 	I915_ENGINE_CLASS_RENDER	= 0,
+
+	/**
+	 * @I915_ENGINE_CLASS_COPY:
+	 *
+	 * Copy engines (also referred to as "blitters") support instructions
+	 * that move blocks of data from one location in memory to another,
+	 * or that fill a specified location of memory with fixed data.
+	 * Copy engines can perform pre-defined logical or bitwise operations
+	 * on the source, destination, or pattern data.
+	 */
 	I915_ENGINE_CLASS_COPY		= 1,
+
+	/**
+	 * @I915_ENGINE_CLASS_VIDEO:
+	 *
+	 * Video engines (also referred to as "bit stream decode" (BSD) or
+	 * "vdbox") support instructions that perform fixed-function media
+	 * decode and encode.
+	 */
 	I915_ENGINE_CLASS_VIDEO		= 2,
+
+	/**
+	 * @I915_ENGINE_CLASS_VIDEO_ENHANCE:
+	 *
+	 * Video enhancement engines (also referred to as "vebox") support
+	 * instructions related to image enhancement.
+	 */
 	I915_ENGINE_CLASS_VIDEO_ENHANCE	= 3,
 
-	/* should be kept compact */
+	/* Values in this enum should be kept compact. */
 
+	/**
+	 * @I915_ENGINE_CLASS_INVALID:
+	 *
+	 * Placeholder value to represent an invalid engine class assignment.
+	 */
 	I915_ENGINE_CLASS_INVALID	= -1
 };
 
-- 
2.35.1


  reply	other threads:[~2022-04-28  4:19 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-04-28  4:19 [Intel-gfx] [PATCH v2 0/4] i915: Turn on compute engine support Matt Roper
2022-04-28  4:19 ` Matt Roper [this message]
2022-04-28 12:59   ` [Intel-gfx] [PATCH v2 1/4] drm/i915/uapi: Add kerneldoc for engine class enum Andi Shyti
2022-04-28  4:19 ` [Intel-gfx] [PATCH v2 2/4] drm/i915/xehp: Add register for compute engine's MMIO-based TLB invalidation Matt Roper
2022-04-28  8:34   ` Tvrtko Ursulin
2022-04-28 12:13   ` Kumar Valsan, Prathap
2022-04-28  4:19 ` [Intel-gfx] [PATCH v2 3/4] drm/i915/xehp: Add compute engine ABI Matt Roper
2022-04-28  7:58   ` Tvrtko Ursulin
2022-04-28 13:04   ` Andi Shyti
2022-04-28  4:19 ` [Intel-gfx] [PATCH v2 4/4] drm/i915: Xe_HP SDV and DG2 have up to 4 CCS engines Matt Roper
2022-04-28  4:32 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for i915: Turn on compute engine support (rev4) Patchwork
2022-04-28  4:55 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-04-28  6:18 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2022-04-29 21:47   ` Matt Roper
2022-04-29 21:23 ` [Intel-gfx] [PATCH v2 0/4] i915: Turn on compute engine support Jordan Justen

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