Re: [Intel-gfx] [PATCH v2 2/4] drm/i915/xehp: Add register for compute engine's MMIO-based TLB invalidation

[Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>]

On 28/04/2022 05:19, Matt Roper wrote:
> Compute engines have a separate register that the driver should use to
> perform MMIO-based TLB invalidation.
> 
> Note that the term "context" in this register's bspec description is
> used to refer to the engine instance (in the same way "context" is used
> on bspec 46167).
> 
> Bspec: 43930
> Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>

Happy even a blind chicken (me) managed to pick on this piece of 
correctness. :)

Acked-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Prathap please r-b since you were the authoritative source in this case.

Regards,

Tvrtko

> ---
>   drivers/gpu/drm/i915/gt/intel_gt.c      | 1 +
>   drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
>   2 files changed, 2 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> index 92394f13b42f..53307ca0eed0 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -1175,6 +1175,7 @@ void intel_gt_invalidate_tlbs(struct intel_gt *gt)
>   		[VIDEO_DECODE_CLASS]		= GEN12_VD_TLB_INV_CR,
>   		[VIDEO_ENHANCEMENT_CLASS]	= GEN12_VE_TLB_INV_CR,
>   		[COPY_ENGINE_CLASS]		= GEN12_BLT_TLB_INV_CR,
> +		[COMPUTE_CLASS]			= GEN12_COMPCTX_TLB_INV_CR,
>   	};
>   	struct drm_i915_private *i915 = gt->i915;
>   	struct intel_uncore *uncore = gt->uncore;
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index a39718a40cc3..a0a49c16babd 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -1007,6 +1007,7 @@
>   #define GEN12_VD_TLB_INV_CR			_MMIO(0xcedc)
>   #define GEN12_VE_TLB_INV_CR			_MMIO(0xcee0)
>   #define GEN12_BLT_TLB_INV_CR			_MMIO(0xcee4)
> +#define GEN12_COMPCTX_TLB_INV_CR		_MMIO(0xcf04)
>   
>   #define GEN12_MERT_MOD_CTRL			_MMIO(0xcf28)
>   #define RENDER_MOD_CTRL				_MMIO(0xcf2c)