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From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 1/3] drm/i915: Initialize eDP source rates after per-panel VBT parsing
Date: Wed,  1 Jun 2022 18:19:05 +0300	[thread overview]
Message-ID: <20220601151907.18725-2-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20220601151907.18725-1-ville.syrjala@linux.intel.com>

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We'll need to know the VBT panel_type before we can determine the
maximum link rate for eDP. To that end move
intel_dp_set_source_rates() & co. to be called after the per-panel
VBT parsing has been done.

I'm not immediately spotting anything that would consult the link
rate arrays before this, so seems safe enough.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 10 ++++------
 1 file changed, 4 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index b8e2d3cd4d68..03af93ef9e93 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2852,9 +2852,6 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp)
 		intel_dp_set_sink_rates(intel_dp);
 	intel_dp_set_max_sink_lane_count(intel_dp);
 
-	intel_dp_set_common_rates(intel_dp);
-	intel_dp_reset_max_link_params(intel_dp);
-
 	/* Read the eDP DSC DPCD registers */
 	if (DISPLAY_VER(dev_priv) >= 10)
 		intel_dp_get_dsc_sink_cap(intel_dp);
@@ -5342,11 +5339,8 @@ intel_dp_init_connector(struct intel_digital_port *dig_port,
 		type = DRM_MODE_CONNECTOR_DisplayPort;
 	}
 
-	intel_dp_set_source_rates(intel_dp);
 	intel_dp_set_default_sink_rates(intel_dp);
 	intel_dp_set_default_max_sink_lane_count(intel_dp);
-	intel_dp_set_common_rates(intel_dp);
-	intel_dp_reset_max_link_params(intel_dp);
 
 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		intel_dp->pps.active_pipe = vlv_active_pipe(intel_dp);
@@ -5384,6 +5378,10 @@ intel_dp_init_connector(struct intel_digital_port *dig_port,
 		goto fail;
 	}
 
+	intel_dp_set_source_rates(intel_dp);
+	intel_dp_set_common_rates(intel_dp);
+	intel_dp_reset_max_link_params(intel_dp);
+
 	intel_dp_add_properties(intel_dp, connector);
 
 	if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
-- 
2.35.1


  reply	other threads:[~2022-06-01 15:19 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-06-01 15:19 [Intel-gfx] [PATCH 0/3] drm/i915: Parse more eDP link rate stuff from VBT Ville Syrjala
2022-06-01 15:19 ` Ville Syrjala [this message]
2022-06-02  9:27   ` [Intel-gfx] [PATCH 1/3] drm/i915: Initialize eDP source rates after per-panel VBT parsing Jani Nikula
2022-06-03 16:58   ` [Intel-gfx] [PATCH v2 " Ville Syrjala
2022-06-01 15:19 ` [Intel-gfx] [PATCH 2/3] drm/i915: Update eDP fast link training link rate parsing Ville Syrjala
2022-06-02  9:38   ` Jani Nikula
2022-06-02 17:57     ` Ville Syrjälä
2022-06-02 20:56   ` [Intel-gfx] [PATCH v2 " Ville Syrjala
2022-06-03  8:01     ` Jani Nikula
2022-06-01 15:19 ` [Intel-gfx] [PATCH 3/3] drm/i915: Parse max link rate from the eDP BDB block Ville Syrjala
2022-06-02  9:43   ` Jani Nikula
2022-06-02 20:57   ` [Intel-gfx] [PATCH v2 " Ville Syrjala
2022-06-03  8:02     ` Jani Nikula
2022-06-01 17:11 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Parse more eDP link rate stuff from VBT Patchwork
2022-06-01 22:08 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2022-06-02 21:29 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Parse more eDP link rate stuff from VBT (rev3) Patchwork
2022-06-03  1:10 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2022-06-04  0:27 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Parse more eDP link rate stuff from VBT (rev4) Patchwork
2022-06-04 16:33 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Parse more eDP link rate stuff from VBT (rev5) Patchwork
2022-06-04 17:55 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork

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