Re: [Intel-gfx] [PATCH 1/3] drm/i915: Initialize eDP source rates after per-panel VBT parsing

[Jani Nikula <jani.nikula@linux.intel.com>]

On Wed, 01 Jun 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> We'll need to know the VBT panel_type before we can determine the
> maximum link rate for eDP. To that end move
> intel_dp_set_source_rates() & co. to be called after the per-panel
> VBT parsing has been done.
>
> I'm not immediately spotting anything that would consult the link
> rate arrays before this, so seems safe enough.

Cc: Imre

I guess these are some of the reasons we have them there:

3f61ef9777c0 ("drm/i915/dp: Ensure sink rate values are always valid")
bedcaddadd22 ("drm/i915/dp: Ensure sink/link max lane count values are always valid")
9ad87de47356 ("drm/i915/dp: Ensure max link params are always valid")

But I can't see why they'd need to be so early. *knocks wood*

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 10 ++++------
>  1 file changed, 4 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index b8e2d3cd4d68..03af93ef9e93 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2852,9 +2852,6 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp)
>  		intel_dp_set_sink_rates(intel_dp);
>  	intel_dp_set_max_sink_lane_count(intel_dp);
>  
> -	intel_dp_set_common_rates(intel_dp);
> -	intel_dp_reset_max_link_params(intel_dp);
> -
>  	/* Read the eDP DSC DPCD registers */
>  	if (DISPLAY_VER(dev_priv) >= 10)
>  		intel_dp_get_dsc_sink_cap(intel_dp);
> @@ -5342,11 +5339,8 @@ intel_dp_init_connector(struct intel_digital_port *dig_port,
>  		type = DRM_MODE_CONNECTOR_DisplayPort;
>  	}
>  
> -	intel_dp_set_source_rates(intel_dp);
>  	intel_dp_set_default_sink_rates(intel_dp);
>  	intel_dp_set_default_max_sink_lane_count(intel_dp);
> -	intel_dp_set_common_rates(intel_dp);
> -	intel_dp_reset_max_link_params(intel_dp);
>  
>  	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>  		intel_dp->pps.active_pipe = vlv_active_pipe(intel_dp);
> @@ -5384,6 +5378,10 @@ intel_dp_init_connector(struct intel_digital_port *dig_port,
>  		goto fail;
>  	}
>  
> +	intel_dp_set_source_rates(intel_dp);
> +	intel_dp_set_common_rates(intel_dp);
> +	intel_dp_reset_max_link_params(intel_dp);
> +
>  	intel_dp_add_properties(intel_dp, connector);
>  
>  	if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {

-- 
Jani Nikula, Intel Open Source Graphics Center