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From: Anusha Srivatsa <anusha.srivatsa@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 1/4] drm/i915/display: Add CDCLK actions to intel_cdclk_state
Date: Wed, 27 Jul 2022 16:26:40 -0700	[thread overview]
Message-ID: <20220727232643.533884-2-anusha.srivatsa@intel.com> (raw)
In-Reply-To: <20220727232643.533884-1-anusha.srivatsa@intel.com>

This is a prep patch for what the rest of the series does.

Add existing actions that change cdclk - squash, crawl, modeset to
intel_cdclk_state so we have access to the cdclk values
that are in transition.

Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.h | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
index b535cf6a7d9e..43835688ee02 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.h
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
@@ -15,6 +15,14 @@ struct drm_i915_private;
 struct intel_atomic_state;
 struct intel_crtc_state;
 
+enum cdclk_actions {
+	INTEL_CDCLK_MODESET = 0,
+	INTEL_CDCLK_SQUASH,
+	INTEL_CDCLK_CRAWL,
+	INTEL_CDCLK_NOOP,
+	MAX_CDCLK_ACTIONS
+};
+
 struct intel_cdclk_config {
 	unsigned int cdclk, vco, ref, bypass;
 	u8 voltage_level;
@@ -51,6 +59,11 @@ struct intel_cdclk_state {
 
 	/* bitmask of active pipes */
 	u8 active_pipes;
+
+	struct cdclk_step {
+		enum cdclk_actions action;
+		u32 cdclk;
+	} steps[MAX_CDCLK_ACTIONS];
 };
 
 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);
-- 
2.25.1


  reply	other threads:[~2022-07-27 23:27 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-07-27 23:26 [Intel-gfx] [PATCH 0/4] Move CDCLK checks to atomic check phase Anusha Srivatsa
2022-07-27 23:26 ` Anusha Srivatsa [this message]
2022-07-27 23:26 ` [Intel-gfx] [PATCH 2/4] drm/i915/display: s/intel_cdclk_can_squash/intel_cdclk_squash Anusha Srivatsa
2022-07-27 23:26 ` [Intel-gfx] [PATCH 3/4] drm/i915/display: s/intel_cdclk_can_crawl/intel_cdclk_crawl Anusha Srivatsa
2022-07-27 23:26 ` [Intel-gfx] [PATCH 4/4] drm/i915/display: Add cdclk checks to atomic check Anusha Srivatsa
2022-07-27 23:52 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Move CDCLK checks to atomic check phase Patchwork
2022-07-27 23:52 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-07-28  0:13 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
  -- strict thread matches above, loose matches on Subject: below --
2022-08-20  0:58 [Intel-gfx] [PATCH 0/4] CDCLK churn: move checks to atomic check Anusha Srivatsa
2022-08-20  0:58 ` [Intel-gfx] [PATCH 1/4] drm/i915/display: Add CDCLK actions to intel_cdclk_state Anusha Srivatsa
2022-09-14 20:00   ` Navare, Manasi
2022-09-14 21:22   ` Ville Syrjälä
2022-09-14 21:42     ` Ville Syrjälä
2022-09-14 21:58       ` Srivatsa, Anusha
2022-09-15  6:05         ` Ville Syrjälä
2022-03-15 19:47 [Intel-gfx] [PATCH 0/5] Add CDCLK checks to atomic check phase Anusha Srivatsa
2022-03-15 19:47 ` [Intel-gfx] [PATCH 1/4] drm/i915/display: Add CDCLK actions to intel_cdclk_state Anusha Srivatsa
2022-03-11  7:04 [Intel-gfx] [PATCH 0/5] Add CDCLK checks to atomic check phase Anusha Srivatsa
2022-03-11  7:04 ` [Intel-gfx] [PATCH 1/4] drm/i915/display: Add CDCLK actions to intel_cdclk_state Anusha Srivatsa

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