public inbox for intel-gfx@lists.freedesktop.org
 help / color / mirror / Atom feed
From: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v2 11/21] drm/i915/mtl: Add DP AUX support on TypeC ports
Date: Thu, 18 Aug 2022 16:41:52 -0700	[thread overview]
Message-ID: <20220818234202.451742-12-radhakrishna.sripada@intel.com> (raw)
In-Reply-To: <20220818234202.451742-1-radhakrishna.sripada@intel.com>

From: Imre Deak <imre.deak@intel.com>

On MTL TypeC ports the AUX_CH_CTL and AUX_CH_DATA addresses have
changed wrt. previous platforms, adjust the code accordingly.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp_aux.c | 45 ++++++++++++++++++++-
 drivers/gpu/drm/i915/i915_reg.h             |  9 +++++
 2 files changed, 53 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c
index 40c4bdd9cb26..10616e18dc18 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
@@ -637,6 +637,46 @@ static i915_reg_t tgl_aux_data_reg(struct intel_dp *intel_dp, int index)
 	}
 }
 
+static i915_reg_t xelpdp_aux_ctl_reg(struct intel_dp *intel_dp)
+{
+	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+	enum aux_ch aux_ch = dig_port->aux_ch;
+
+	switch (aux_ch) {
+	case AUX_CH_A:
+	case AUX_CH_B:
+	case AUX_CH_USBC1:
+	case AUX_CH_USBC2:
+	case AUX_CH_USBC3:
+	case AUX_CH_USBC4:
+		return XELPDP_DP_AUX_CH_CTL(aux_ch);
+	default:
+		MISSING_CASE(aux_ch);
+		return XELPDP_DP_AUX_CH_CTL(AUX_CH_A);
+	}
+}
+
+static i915_reg_t xelpdp_aux_data_reg(struct intel_dp *intel_dp, int index)
+{
+	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+	enum aux_ch aux_ch = dig_port->aux_ch;
+
+	switch (aux_ch) {
+	case AUX_CH_A:
+	case AUX_CH_B:
+	case AUX_CH_USBC1:
+	case AUX_CH_USBC2:
+	case AUX_CH_USBC3:
+	case AUX_CH_USBC4:
+		return XELPDP_DP_AUX_CH_DATA(aux_ch, index);
+	default:
+		MISSING_CASE(aux_ch);
+		return XELPDP_DP_AUX_CH_DATA(AUX_CH_A, index);
+	}
+}
+
 void intel_dp_aux_fini(struct intel_dp *intel_dp)
 {
 	if (cpu_latency_qos_request_active(&intel_dp->pm_qos))
@@ -652,7 +692,10 @@ void intel_dp_aux_init(struct intel_dp *intel_dp)
 	struct intel_encoder *encoder = &dig_port->base;
 	enum aux_ch aux_ch = dig_port->aux_ch;
 
-	if (DISPLAY_VER(dev_priv) >= 12) {
+	if (DISPLAY_VER(dev_priv) >= 14) {
+		intel_dp->aux_ch_ctl_reg = xelpdp_aux_ctl_reg;
+		intel_dp->aux_ch_data_reg = xelpdp_aux_data_reg;
+	} else if (DISPLAY_VER(dev_priv) >= 12) {
 		intel_dp->aux_ch_ctl_reg = tgl_aux_ctl_reg;
 		intel_dp->aux_ch_data_reg = tgl_aux_data_reg;
 	} else if (DISPLAY_VER(dev_priv) >= 9) {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 234c17596c3a..04a269fa8717 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3533,6 +3533,15 @@
 						       _XELPDP_USBC3_AUX_CH_CTL, \
 						       _XELPDP_USBC4_AUX_CH_CTL))
 
+#define XELPDP_DP_AUX_CH_DATA(aux_ch, i)	_MMIO(_PICK(aux_ch, \
+						       _DPA_AUX_CH_DATA1, \
+						       _DPB_AUX_CH_DATA1, \
+						       0, /* port/aux_ch C is non-existent */ \
+						       _XELPDP_USBC1_AUX_CH_DATA1, \
+						       _XELPDP_USBC2_AUX_CH_DATA1, \
+						       _XELPDP_USBC3_AUX_CH_DATA1, \
+						       _XELPDP_USBC4_AUX_CH_DATA1) + (i) * 4)
+
 #define   DP_AUX_CH_CTL_SEND_BUSY	    (1 << 31)
 #define   DP_AUX_CH_CTL_DONE		    (1 << 30)
 #define   DP_AUX_CH_CTL_INTERRUPT	    (1 << 29)
-- 
2.25.1


  parent reply	other threads:[~2022-08-18 23:44 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-08-18 23:41 [Intel-gfx] [PATCH v2 00/21] Initial Meteorlake Support Radhakrishna Sripada
2022-08-18 23:41 ` [Intel-gfx] [PATCH v2 01/21] drm/i915: Read graphics/media/display arch version from hw Radhakrishna Sripada
2022-08-19 19:04   ` Matt Roper
2022-08-24 10:10     ` Jani Nikula
2022-08-18 23:41 ` [Intel-gfx] [PATCH v2 02/21] drm/i915: Parse and set stepping for platforms with GMD Radhakrishna Sripada
2022-08-24  8:11   ` Balasubramani Vivekanandan
2022-08-18 23:41 ` [Intel-gfx] [PATCH v2 03/21] drm/i915/mtl: MMIO range is now 4MB Radhakrishna Sripada
2022-08-24 13:25   ` Balasubramani Vivekanandan
2022-08-18 23:41 ` [Intel-gfx] [PATCH v2 04/21] drm/i915/mtl: Don't mask off CCS according to DSS fusing Radhakrishna Sripada
2022-08-24 14:54   ` Balasubramani Vivekanandan
2022-08-18 23:41 ` [Intel-gfx] [PATCH v2 05/21] drm/i915/mtl: Define engine context layouts Radhakrishna Sripada
2022-08-25 10:33   ` Balasubramani Vivekanandan
2022-08-18 23:41 ` [Intel-gfx] [PATCH v2 06/21] drm/i915/mtl: Add PCH support Radhakrishna Sripada
2022-08-18 23:41 ` [Intel-gfx] [PATCH v2 07/21] drm/i915/mtl: Add gmbus and gpio support Radhakrishna Sripada
2022-08-19 19:17   ` Matt Roper
2022-08-18 23:41 ` [Intel-gfx] [PATCH v2 08/21] drm/i915/mtl: Add VBT port and AUX_CH mapping Radhakrishna Sripada
2022-08-18 23:41 ` [Intel-gfx] [PATCH v2 09/21] drm/i915/mtl: Add support for MTL in Display Init sequences Radhakrishna Sripada
2022-08-18 23:41 ` [Intel-gfx] [PATCH v2 10/21] drm/i915/mtl: Add display power wells Radhakrishna Sripada
2022-08-18 23:41 ` Radhakrishna Sripada [this message]
2022-08-18 23:41 ` [Intel-gfx] [PATCH v2 12/21] drm/i915/mtl: Fix rawclk for Meteorlake PCH Radhakrishna Sripada
2022-08-18 23:41 ` [Intel-gfx] [PATCH v2 13/21] drm/i915: Extract wm latency adjustment to its own function Radhakrishna Sripada
2022-08-19 19:26   ` Matt Roper
2022-08-18 23:41 ` [Intel-gfx] [PATCH v2 14/21] drm/i915/mtl: memory latency data from LATENCY_LPX_LPY for WM Radhakrishna Sripada
2022-08-19 19:31   ` Matt Roper
2022-08-18 23:41 ` [Intel-gfx] [PATCH v2 15/21] drm/i915/mtl: Obtain SAGV values from MMIO instead of GT pcode mailbox Radhakrishna Sripada
2022-08-27  0:03   ` Matt Roper
2022-08-18 23:41 ` [Intel-gfx] [PATCH v2 16/21] drm/i915/mtl: Update memory bandwidth parameters Radhakrishna Sripada
2022-08-18 23:41 ` [Intel-gfx] [PATCH v2 17/21] drm/i915/mtl: Update MBUS_DBOX credits Radhakrishna Sripada
2022-08-18 23:41 ` [Intel-gfx] [PATCH v2 18/21] drm/i915/mtl: Reuse adl-p DBUF calculations Radhakrishna Sripada
2022-08-18 23:42 ` [Intel-gfx] [PATCH v2 19/21] drm/i915/display/mtl: Extend MBUS programming Radhakrishna Sripada
2022-08-18 23:42 ` [Intel-gfx] [PATCH v2 20/21] drm/i915/mtl: Update CHICKEN_TRANS* register addresses Radhakrishna Sripada
2022-08-18 23:42 ` [Intel-gfx] [PATCH v2 21/21] drm/i915/mtl: Do not update GV point, mask value Radhakrishna Sripada
2022-08-19 19:46   ` Matt Roper
2022-08-24 21:26 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Initial Meteorlake Support (rev3) Patchwork

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20220818234202.451742-12-radhakrishna.sripada@intel.com \
    --to=radhakrishna.sripada@intel.com \
    --cc=dri-devel@lists.freedesktop.org \
    --cc=intel-gfx@lists.freedesktop.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox