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From: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v2 07/21] drm/i915/mtl: Add gmbus and gpio support
Date: Thu, 18 Aug 2022 16:41:48 -0700	[thread overview]
Message-ID: <20220818234202.451742-8-radhakrishna.sripada@intel.com> (raw)
In-Reply-To: <20220818234202.451742-1-radhakrishna.sripada@intel.com>

Add tables to map the GMBUS pin pairs to GPIO registers and port to DDC.
From spec we have registers GPIO_CTL[1-5] mapped to native display phys and
GPIO_CTL[9-14] are mapped to TC ports.

BSpec: 49306

Original Author: Brian J Lovin
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
 drivers/gpu/drm/i915/display/intel_gmbus.c | 17 +++++++++++++++++
 drivers/gpu/drm/i915/display/intel_gmbus.h |  1 +
 2 files changed, 18 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c
index a6ba7fb72339..542b8b2654be 100644
--- a/drivers/gpu/drm/i915/display/intel_gmbus.c
+++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
@@ -116,6 +116,20 @@ static const struct gmbus_pin gmbus_pins_dg2[] = {
 	[GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
 };
 
+static const struct gmbus_pin gmbus_pins_mtp[] = {
+	[GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
+	[GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
+	[GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
+	[GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
+	[GMBUS_PIN_5_MTP] = { "dpe", GPIOF },
+	[GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
+	[GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK },
+	[GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL },
+	[GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM },
+	[GMBUS_PIN_13_TC5_TGP] = { "tc5", GPION },
+	[GMBUS_PIN_14_TC6_TGP] = { "tc6", GPIOO },
+};
+
 static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *i915,
 					     unsigned int pin)
 {
@@ -128,6 +142,9 @@ static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *i915,
 	} else if (INTEL_PCH_TYPE(i915) >= PCH_DG1) {
 		pins = gmbus_pins_dg1;
 		size = ARRAY_SIZE(gmbus_pins_dg1);
+	} else if (INTEL_PCH_TYPE(i915) >= PCH_MTP) {
+		pins = gmbus_pins_mtp;
+		size = ARRAY_SIZE(gmbus_pins_mtp);
 	} else if (INTEL_PCH_TYPE(i915) >= PCH_ICP) {
 		pins = gmbus_pins_icp;
 		size = ARRAY_SIZE(gmbus_pins_icp);
diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.h b/drivers/gpu/drm/i915/display/intel_gmbus.h
index 8edc2e99cf53..20f704bd4e70 100644
--- a/drivers/gpu/drm/i915/display/intel_gmbus.h
+++ b/drivers/gpu/drm/i915/display/intel_gmbus.h
@@ -24,6 +24,7 @@ struct i2c_adapter;
 #define GMBUS_PIN_2_BXT		2
 #define GMBUS_PIN_3_BXT		3
 #define GMBUS_PIN_4_CNP		4
+#define GMBUS_PIN_5_MTP		5
 #define GMBUS_PIN_9_TC1_ICP	9
 #define GMBUS_PIN_10_TC2_ICP	10
 #define GMBUS_PIN_11_TC3_ICP	11
-- 
2.25.1


  parent reply	other threads:[~2022-08-18 23:44 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-08-18 23:41 [Intel-gfx] [PATCH v2 00/21] Initial Meteorlake Support Radhakrishna Sripada
2022-08-18 23:41 ` [Intel-gfx] [PATCH v2 01/21] drm/i915: Read graphics/media/display arch version from hw Radhakrishna Sripada
2022-08-19 19:04   ` Matt Roper
2022-08-24 10:10     ` Jani Nikula
2022-08-18 23:41 ` [Intel-gfx] [PATCH v2 02/21] drm/i915: Parse and set stepping for platforms with GMD Radhakrishna Sripada
2022-08-24  8:11   ` Balasubramani Vivekanandan
2022-08-18 23:41 ` [Intel-gfx] [PATCH v2 03/21] drm/i915/mtl: MMIO range is now 4MB Radhakrishna Sripada
2022-08-24 13:25   ` Balasubramani Vivekanandan
2022-08-18 23:41 ` [Intel-gfx] [PATCH v2 04/21] drm/i915/mtl: Don't mask off CCS according to DSS fusing Radhakrishna Sripada
2022-08-24 14:54   ` Balasubramani Vivekanandan
2022-08-18 23:41 ` [Intel-gfx] [PATCH v2 05/21] drm/i915/mtl: Define engine context layouts Radhakrishna Sripada
2022-08-25 10:33   ` Balasubramani Vivekanandan
2022-08-18 23:41 ` [Intel-gfx] [PATCH v2 06/21] drm/i915/mtl: Add PCH support Radhakrishna Sripada
2022-08-18 23:41 ` Radhakrishna Sripada [this message]
2022-08-19 19:17   ` [Intel-gfx] [PATCH v2 07/21] drm/i915/mtl: Add gmbus and gpio support Matt Roper
2022-08-18 23:41 ` [Intel-gfx] [PATCH v2 08/21] drm/i915/mtl: Add VBT port and AUX_CH mapping Radhakrishna Sripada
2022-08-18 23:41 ` [Intel-gfx] [PATCH v2 09/21] drm/i915/mtl: Add support for MTL in Display Init sequences Radhakrishna Sripada
2022-08-18 23:41 ` [Intel-gfx] [PATCH v2 10/21] drm/i915/mtl: Add display power wells Radhakrishna Sripada
2022-08-18 23:41 ` [Intel-gfx] [PATCH v2 11/21] drm/i915/mtl: Add DP AUX support on TypeC ports Radhakrishna Sripada
2022-08-18 23:41 ` [Intel-gfx] [PATCH v2 12/21] drm/i915/mtl: Fix rawclk for Meteorlake PCH Radhakrishna Sripada
2022-08-18 23:41 ` [Intel-gfx] [PATCH v2 13/21] drm/i915: Extract wm latency adjustment to its own function Radhakrishna Sripada
2022-08-19 19:26   ` Matt Roper
2022-08-18 23:41 ` [Intel-gfx] [PATCH v2 14/21] drm/i915/mtl: memory latency data from LATENCY_LPX_LPY for WM Radhakrishna Sripada
2022-08-19 19:31   ` Matt Roper
2022-08-18 23:41 ` [Intel-gfx] [PATCH v2 15/21] drm/i915/mtl: Obtain SAGV values from MMIO instead of GT pcode mailbox Radhakrishna Sripada
2022-08-27  0:03   ` Matt Roper
2022-08-18 23:41 ` [Intel-gfx] [PATCH v2 16/21] drm/i915/mtl: Update memory bandwidth parameters Radhakrishna Sripada
2022-08-18 23:41 ` [Intel-gfx] [PATCH v2 17/21] drm/i915/mtl: Update MBUS_DBOX credits Radhakrishna Sripada
2022-08-18 23:41 ` [Intel-gfx] [PATCH v2 18/21] drm/i915/mtl: Reuse adl-p DBUF calculations Radhakrishna Sripada
2022-08-18 23:42 ` [Intel-gfx] [PATCH v2 19/21] drm/i915/display/mtl: Extend MBUS programming Radhakrishna Sripada
2022-08-18 23:42 ` [Intel-gfx] [PATCH v2 20/21] drm/i915/mtl: Update CHICKEN_TRANS* register addresses Radhakrishna Sripada
2022-08-18 23:42 ` [Intel-gfx] [PATCH v2 21/21] drm/i915/mtl: Do not update GV point, mask value Radhakrishna Sripada
2022-08-19 19:46   ` Matt Roper
2022-08-24 21:26 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Initial Meteorlake Support (rev3) Patchwork

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