* [Intel-gfx] [PATCH] Revert "drm/i915/guc: Add delay to disable scheduling after pin count goes to zero"
@ 2022-08-19 12:39 Matthew Auld
2022-08-19 13:25 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for " Patchwork
` (3 more replies)
0 siblings, 4 replies; 7+ messages in thread
From: Matthew Auld @ 2022-08-19 12:39 UTC (permalink / raw)
To: intel-gfx; +Cc: Alan Previn
This reverts commit 6a079903847cce1dd06345127d2a32f26d2cd9c6.
Everything in CI using GuC is now timing out[1], and killing the machine
with this change (perhaps a deadlock?). CI was recently on fire due to
some changes coming in from -rc1, so likely the pre-merge CI results for
this series were invalid? For now just revert, unless GuC experts
already have a fix in mind.
[1] https://intel-gfx-ci.01.org/tree/drm-tip/index.html?
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Cc: Alan Previn <alan.previn.teres.alexis@intel.com>
Cc: John Harrison <John.C.Harrison@Intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 2 +-
drivers/gpu/drm/i915/gt/intel_context.h | 8 -
drivers/gpu/drm/i915/gt/intel_context_types.h | 7 -
drivers/gpu/drm/i915/gt/uc/intel_guc.h | 17 +-
.../gpu/drm/i915/gt/uc/intel_guc_debugfs.c | 60 -------
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 154 +++---------------
drivers/gpu/drm/i915/i915_selftest.h | 2 -
7 files changed, 27 insertions(+), 223 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index df7fd1b019ec..dabdfe09f5e5 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -1454,7 +1454,7 @@ static void engines_idle_release(struct i915_gem_context *ctx,
int err;
/* serialises with execbuf */
- intel_context_close(ce);
+ set_bit(CONTEXT_CLOSED_BIT, &ce->flags);
if (!intel_context_pin_if_active(ce))
continue;
diff --git a/drivers/gpu/drm/i915/gt/intel_context.h b/drivers/gpu/drm/i915/gt/intel_context.h
index f96420f0b5bb..8e2d70630c49 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.h
+++ b/drivers/gpu/drm/i915/gt/intel_context.h
@@ -276,14 +276,6 @@ static inline bool intel_context_is_barrier(const struct intel_context *ce)
return test_bit(CONTEXT_BARRIER_BIT, &ce->flags);
}
-static inline void intel_context_close(struct intel_context *ce)
-{
- set_bit(CONTEXT_CLOSED_BIT, &ce->flags);
-
- if (ce->ops->close)
- ce->ops->close(ce);
-}
-
static inline bool intel_context_is_closed(const struct intel_context *ce)
{
return test_bit(CONTEXT_CLOSED_BIT, &ce->flags);
diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h b/drivers/gpu/drm/i915/gt/intel_context_types.h
index 86ac84e2edb9..04eacae1aca5 100644
--- a/drivers/gpu/drm/i915/gt/intel_context_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
@@ -43,8 +43,6 @@ struct intel_context_ops {
void (*revoke)(struct intel_context *ce, struct i915_request *rq,
unsigned int preempt_timeout_ms);
- void (*close)(struct intel_context *ce);
-
int (*pre_pin)(struct intel_context *ce, struct i915_gem_ww_ctx *ww, void **vaddr);
int (*pin)(struct intel_context *ce, void *vaddr);
void (*unpin)(struct intel_context *ce);
@@ -210,11 +208,6 @@ struct intel_context {
* each priority bucket
*/
u32 prio_count[GUC_CLIENT_PRIORITY_NUM];
- /**
- * @sched_disable_delay: worker to disable scheduling on this
- * context
- */
- struct delayed_work sched_disable_delay;
} guc_state;
struct {
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index 944b549b8797..804133df1ac9 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -112,10 +112,6 @@ struct intel_guc {
* refs
*/
struct list_head guc_id_list;
- /**
- * @guc_ids_in_use: Number single-lrc guc_ids in use
- */
- u16 guc_ids_in_use;
/**
* @destroyed_contexts: list of contexts waiting to be destroyed
* (deregistered with the GuC)
@@ -136,16 +132,6 @@ struct intel_guc {
* @reset_fail_mask: mask of engines that failed to reset
*/
intel_engine_mask_t reset_fail_mask;
- /**
- * @sched_disable_delay_ms: schedule disable delay, in ms, for
- * contexts
- */
- u64 sched_disable_delay_ms;
- /**
- * @sched_disable_gucid_threshold: threshold of min remaining available
- * guc_ids before we start bypassing the schedule disable delay
- */
- int sched_disable_gucid_threshold;
} submission_state;
/**
@@ -475,10 +461,9 @@ void intel_guc_submission_reset_finish(struct intel_guc *guc);
void intel_guc_submission_cancel_requests(struct intel_guc *guc);
void intel_guc_load_status(struct intel_guc *guc, struct drm_printer *p);
-void intel_guc_dump_time_info(struct intel_guc *guc, struct drm_printer *p);
void intel_guc_write_barrier(struct intel_guc *guc);
-int intel_guc_sched_disable_gucid_threshold_max(struct intel_guc *guc);
+void intel_guc_dump_time_info(struct intel_guc *guc, struct drm_printer *p);
#endif
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.c
index c91b150bb7ac..25f09a420561 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.c
@@ -71,72 +71,12 @@ static bool intel_eval_slpc_support(void *data)
return intel_guc_slpc_is_used(guc);
}
-static int guc_sched_disable_delay_ms_get(void *data, u64 *val)
-{
- struct intel_guc *guc = data;
-
- if (!intel_guc_submission_is_used(guc))
- return -ENODEV;
-
- *val = guc->submission_state.sched_disable_delay_ms;
-
- return 0;
-}
-
-static int guc_sched_disable_delay_ms_set(void *data, u64 val)
-{
- struct intel_guc *guc = data;
-
- if (!intel_guc_submission_is_used(guc))
- return -ENODEV;
-
- guc->submission_state.sched_disable_delay_ms = val;
-
- return 0;
-}
-DEFINE_SIMPLE_ATTRIBUTE(guc_sched_disable_delay_ms_fops,
- guc_sched_disable_delay_ms_get,
- guc_sched_disable_delay_ms_set, "%lld\n");
-
-static int guc_sched_disable_gucid_threshold_get(void *data, u64 *val)
-{
- struct intel_guc *guc = data;
-
- if (!intel_guc_submission_is_used(guc))
- return -ENODEV;
-
- *val = guc->submission_state.sched_disable_gucid_threshold;
- return 0;
-}
-
-static int guc_sched_disable_gucid_threshold_set(void *data, u64 val)
-{
- struct intel_guc *guc = data;
-
- if (!intel_guc_submission_is_used(guc))
- return -ENODEV;
-
- if (val > intel_guc_sched_disable_gucid_threshold_max(guc))
- guc->submission_state.sched_disable_gucid_threshold =
- intel_guc_sched_disable_gucid_threshold_max(guc);
- else
- guc->submission_state.sched_disable_gucid_threshold = val;
-
- return 0;
-}
-DEFINE_SIMPLE_ATTRIBUTE(guc_sched_disable_gucid_threshold_fops,
- guc_sched_disable_gucid_threshold_get,
- guc_sched_disable_gucid_threshold_set, "%lld\n");
-
void intel_guc_debugfs_register(struct intel_guc *guc, struct dentry *root)
{
static const struct intel_gt_debugfs_file files[] = {
{ "guc_info", &guc_info_fops, NULL },
{ "guc_registered_contexts", &guc_registered_contexts_fops, NULL },
{ "guc_slpc_info", &guc_slpc_info_fops, &intel_eval_slpc_support},
- { "guc_sched_disable_delay_ms", &guc_sched_disable_delay_ms_fops, NULL },
- { "guc_sched_disable_gucid_threshold", &guc_sched_disable_gucid_threshold_fops,
- NULL },
};
if (!intel_guc_is_supported(guc))
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index a0cebb4590e9..0d56b615bf78 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -65,13 +65,7 @@
* corresponding G2H returns indicating the scheduling disable operation has
* completed it is safe to unpin the context. While a disable is in flight it
* isn't safe to resubmit the context so a fence is used to stall all future
- * requests of that context until the G2H is returned. Because this interaction
- * with the GuC takes a non-zero amount of time we delay the disabling of
- * scheduling after the pin count goes to zero by a configurable period of time
- * (see SCHED_DISABLE_DELAY_MS). The thought is this gives the user a window of
- * time to resubmit something on the context before doing this costly operation.
- * This delay is only done if the context isn't closed and the guc_id usage is
- * less than a threshold (see NUM_SCHED_DISABLE_GUC_IDS_THRESHOLD).
+ * requests of that context until the G2H is returned.
*
* Context deregistration:
* Before a context can be destroyed or if we steal its guc_id we must
@@ -1995,9 +1989,6 @@ static int new_guc_id(struct intel_guc *guc, struct intel_context *ce)
if (unlikely(ret < 0))
return ret;
- if (!intel_context_is_parent(ce))
- ++guc->submission_state.guc_ids_in_use;
-
ce->guc_id.id = ret;
return 0;
}
@@ -2007,16 +1998,14 @@ static void __release_guc_id(struct intel_guc *guc, struct intel_context *ce)
GEM_BUG_ON(intel_context_is_child(ce));
if (!context_guc_id_invalid(ce)) {
- if (intel_context_is_parent(ce)) {
+ if (intel_context_is_parent(ce))
bitmap_release_region(guc->submission_state.guc_ids_bitmap,
ce->guc_id.id,
order_base_2(ce->parallel.number_children
+ 1));
- } else {
- --guc->submission_state.guc_ids_in_use;
+ else
ida_simple_remove(&guc->submission_state.guc_ids,
ce->guc_id.id);
- }
clr_ctx_id_mapping(guc, ce->guc_id.id);
set_context_guc_id_invalid(ce);
}
@@ -3004,98 +2993,41 @@ guc_context_revoke(struct intel_context *ce, struct i915_request *rq,
}
}
-static void guc_context_sched_disable(struct intel_context *ce);
-
-static void do_sched_disable(struct intel_guc *guc, struct intel_context *ce,
- unsigned long flags)
- __releases(ce->guc_state.lock)
+static void guc_context_sched_disable(struct intel_context *ce)
{
+ struct intel_guc *guc = ce_to_guc(ce);
+ unsigned long flags;
struct intel_runtime_pm *runtime_pm = &ce->engine->gt->i915->runtime_pm;
intel_wakeref_t wakeref;
+ u16 guc_id;
- lockdep_assert_held(&ce->guc_state.lock);
-
- spin_unlock_irqrestore(&ce->guc_state.lock, flags);
-
- with_intel_runtime_pm(runtime_pm, wakeref)
- guc_context_sched_disable(ce);
-}
-
-static bool bypass_sched_disable(struct intel_guc *guc,
- struct intel_context *ce)
-{
- lockdep_assert_held(&ce->guc_state.lock);
GEM_BUG_ON(intel_context_is_child(ce));
- if (submission_disabled(guc) || context_guc_id_invalid(ce) ||
- !ctx_id_mapped(guc, ce->guc_id.id)) {
- clr_context_enabled(ce);
- return true;
- }
-
- return !context_enabled(ce);
-}
-
-static void __delay_sched_disable(struct work_struct *wrk)
-{
- struct intel_context *ce =
- container_of(wrk, typeof(*ce), guc_state.sched_disable_delay.work);
- struct intel_guc *guc = ce_to_guc(ce);
- unsigned long flags;
-
spin_lock_irqsave(&ce->guc_state.lock, flags);
- if (bypass_sched_disable(guc, ce)) {
- spin_unlock_irqrestore(&ce->guc_state.lock, flags);
- intel_context_sched_disable_unpin(ce);
- } else {
- do_sched_disable(guc, ce, flags);
- }
-}
-
-static bool guc_id_pressure(struct intel_guc *guc, struct intel_context *ce)
-{
- /*
- * parent contexts are perma-pinned, if we are unpinning do schedule
- * disable immediately.
- */
- if (intel_context_is_parent(ce))
- return true;
-
/*
- * If we are beyond the threshold for avail guc_ids, do schedule disable immediately.
+ * We have to check if the context has been disabled by another thread,
+ * check if submssion has been disabled to seal a race with reset and
+ * finally check if any more requests have been committed to the
+ * context ensursing that a request doesn't slip through the
+ * 'context_pending_disable' fence.
*/
- return guc->submission_state.guc_ids_in_use >
- guc->submission_state.sched_disable_gucid_threshold;
-}
-
-static void guc_context_sched_disable(struct intel_context *ce)
-{
- struct intel_guc *guc = ce_to_guc(ce);
- u64 delay = guc->submission_state.sched_disable_delay_ms;
- unsigned long flags;
-
- spin_lock_irqsave(&ce->guc_state.lock, flags);
-
- if (bypass_sched_disable(guc, ce)) {
- spin_unlock_irqrestore(&ce->guc_state.lock, flags);
- intel_context_sched_disable_unpin(ce);
- } else if (!intel_context_is_closed(ce) && !guc_id_pressure(guc, ce) &&
- delay) {
+ if (unlikely(!context_enabled(ce) || submission_disabled(guc) ||
+ context_has_committed_requests(ce))) {
+ clr_context_enabled(ce);
spin_unlock_irqrestore(&ce->guc_state.lock, flags);
- mod_delayed_work(system_unbound_wq,
- &ce->guc_state.sched_disable_delay,
- msecs_to_jiffies(delay));
- } else {
- do_sched_disable(guc, ce, flags);
+ goto unpin;
}
-}
+ guc_id = prep_context_pending_disable(ce);
-static void guc_context_close(struct intel_context *ce)
-{
- if (test_bit(CONTEXT_GUC_INIT, &ce->flags) &&
- cancel_delayed_work(&ce->guc_state.sched_disable_delay))
- __delay_sched_disable(&ce->guc_state.sched_disable_delay.work);
+ spin_unlock_irqrestore(&ce->guc_state.lock, flags);
+
+ with_intel_runtime_pm(runtime_pm, wakeref)
+ __guc_context_sched_disable(guc, ce, guc_id);
+
+ return;
+unpin:
+ intel_context_sched_disable_unpin(ce);
}
static inline void guc_lrc_desc_unpin(struct intel_context *ce)
@@ -3414,8 +3346,6 @@ static void remove_from_context(struct i915_request *rq)
static const struct intel_context_ops guc_context_ops = {
.alloc = guc_context_alloc,
- .close = guc_context_close,
-
.pre_pin = guc_context_pre_pin,
.pin = guc_context_pin,
.unpin = guc_context_unpin,
@@ -3498,10 +3428,6 @@ static void guc_context_init(struct intel_context *ce)
rcu_read_unlock();
ce->guc_state.prio = map_i915_prio_to_guc_prio(prio);
-
- INIT_DELAYED_WORK(&ce->guc_state.sched_disable_delay,
- __delay_sched_disable);
-
set_bit(CONTEXT_GUC_INIT, &ce->flags);
}
@@ -3539,9 +3465,6 @@ static int guc_request_alloc(struct i915_request *rq)
if (unlikely(!test_bit(CONTEXT_GUC_INIT, &ce->flags)))
guc_context_init(ce);
- if (cancel_delayed_work(&ce->guc_state.sched_disable_delay))
- intel_context_sched_disable_unpin(ce);
-
/*
* Call pin_guc_id here rather than in the pinning step as with
* dma_resv, contexts can be repeatedly pinned / unpinned trashing the
@@ -3672,8 +3595,6 @@ static int guc_virtual_context_alloc(struct intel_context *ce)
static const struct intel_context_ops virtual_guc_context_ops = {
.alloc = guc_virtual_context_alloc,
- .close = guc_context_close,
-
.pre_pin = guc_virtual_context_pre_pin,
.pin = guc_virtual_context_pin,
.unpin = guc_virtual_context_unpin,
@@ -3763,8 +3684,6 @@ static void guc_child_context_destroy(struct kref *kref)
static const struct intel_context_ops virtual_parent_context_ops = {
.alloc = guc_virtual_context_alloc,
- .close = guc_context_close,
-
.pre_pin = guc_context_pre_pin,
.pin = guc_parent_context_pin,
.unpin = guc_parent_context_unpin,
@@ -4295,26 +4214,6 @@ static bool __guc_submission_selected(struct intel_guc *guc)
return i915->params.enable_guc & ENABLE_GUC_SUBMISSION;
}
-int intel_guc_sched_disable_gucid_threshold_max(struct intel_guc *guc)
-{
- return guc->submission_state.num_guc_ids - NUMBER_MULTI_LRC_GUC_ID(guc);
-}
-
-/*
- * This default value of 33 milisecs (+1 milisec round up) ensures 30fps or higher
- * workloads are able to enjoy the latency reduction when delaying the schedule-disable
- * operation. This matches the 30fps game-render + encode (real world) workload this
- * knob was tested against.
- */
-#define SCHED_DISABLE_DELAY_MS 34
-
-/*
- * A threshold of 75% is a reasonable starting point considering that real world apps
- * generally don't get anywhere near this.
- */
-#define NUM_SCHED_DISABLE_GUCIDS_DEFAULT_THRESHOLD(__guc) \
- (((intel_guc_sched_disable_gucid_threshold_max(guc)) * 3) / 4)
-
void intel_guc_submission_init_early(struct intel_guc *guc)
{
xa_init_flags(&guc->context_lookup, XA_FLAGS_LOCK_IRQ);
@@ -4331,10 +4230,7 @@ void intel_guc_submission_init_early(struct intel_guc *guc)
spin_lock_init(&guc->timestamp.lock);
INIT_DELAYED_WORK(&guc->timestamp.work, guc_timestamp_ping);
- guc->submission_state.sched_disable_delay_ms = SCHED_DISABLE_DELAY_MS;
guc->submission_state.num_guc_ids = GUC_MAX_CONTEXT_ID;
- guc->submission_state.sched_disable_gucid_threshold =
- NUM_SCHED_DISABLE_GUCIDS_DEFAULT_THRESHOLD(guc);
guc->submission_supported = __guc_submission_supported(guc);
guc->submission_selected = __guc_submission_selected(guc);
}
diff --git a/drivers/gpu/drm/i915/i915_selftest.h b/drivers/gpu/drm/i915/i915_selftest.h
index bdf3e22c0a34..f54de0499be7 100644
--- a/drivers/gpu/drm/i915/i915_selftest.h
+++ b/drivers/gpu/drm/i915/i915_selftest.h
@@ -92,14 +92,12 @@ int __i915_subtests(const char *caller,
T, ARRAY_SIZE(T), data)
#define i915_live_subtests(T, data) ({ \
typecheck(struct drm_i915_private *, data); \
- (data)->gt[0]->uc.guc.submission_state.sched_disable_delay_ms = 0; \
__i915_subtests(__func__, \
__i915_live_setup, __i915_live_teardown, \
T, ARRAY_SIZE(T), data); \
})
#define intel_gt_live_subtests(T, data) ({ \
typecheck(struct intel_gt *, data); \
- (data)->uc.guc.submission_state.sched_disable_delay_ms = 0; \
__i915_subtests(__func__, \
__intel_gt_live_setup, __intel_gt_live_teardown, \
T, ARRAY_SIZE(T), data); \
--
2.37.2
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Revert "drm/i915/guc: Add delay to disable scheduling after pin count goes to zero"
2022-08-19 12:39 [Intel-gfx] [PATCH] Revert "drm/i915/guc: Add delay to disable scheduling after pin count goes to zero" Matthew Auld
@ 2022-08-19 13:25 ` Patchwork
2022-08-19 13:48 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (2 subsequent siblings)
3 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2022-08-19 13:25 UTC (permalink / raw)
To: Matthew Auld; +Cc: intel-gfx
== Series Details ==
Series: Revert "drm/i915/guc: Add delay to disable scheduling after pin count goes to zero"
URL : https://patchwork.freedesktop.org/series/107502/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 7+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for Revert "drm/i915/guc: Add delay to disable scheduling after pin count goes to zero"
2022-08-19 12:39 [Intel-gfx] [PATCH] Revert "drm/i915/guc: Add delay to disable scheduling after pin count goes to zero" Matthew Auld
2022-08-19 13:25 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for " Patchwork
@ 2022-08-19 13:48 ` Patchwork
2022-08-19 15:46 ` [Intel-gfx] [PATCH] " John Harrison
2022-08-20 13:13 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for " Patchwork
3 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2022-08-19 13:48 UTC (permalink / raw)
To: Matthew Auld; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 13155 bytes --]
== Series Details ==
Series: Revert "drm/i915/guc: Add delay to disable scheduling after pin count goes to zero"
URL : https://patchwork.freedesktop.org/series/107502/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12003 -> Patchwork_107502v1
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/index.html
Participating hosts (30 -> 31)
------------------------------
Additional (6): fi-rkl-11600 bat-dg2-8 bat-adlm-1 bat-adlp-6 bat-jsl-3 bat-dg2-10
Missing (5): fi-kbl-soraka bat-dg1-6 bat-dg1-5 fi-ilk-650 bat-rplp-1
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_107502v1:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@gt_lrc:
- {bat-dg2-9}: NOTRUN -> [INCOMPLETE][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/bat-dg2-9/igt@i915_selftest@live@gt_lrc.html
* igt@i915_selftest@live@workarounds:
- {bat-dg2-10}: NOTRUN -> [DMESG-FAIL][2]
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/bat-dg2-10/igt@i915_selftest@live@workarounds.html
- {bat-dg2-9}: NOTRUN -> [DMESG-FAIL][3]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/bat-dg2-9/igt@i915_selftest@live@workarounds.html
- {bat-dg2-8}: NOTRUN -> [DMESG-FAIL][4]
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/bat-dg2-8/igt@i915_selftest@live@workarounds.html
* igt@i915_suspend@basic-s3-without-i915:
- {bat-dg2-8}: NOTRUN -> [SKIP][5]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/bat-dg2-8/igt@i915_suspend@basic-s3-without-i915.html
* igt@runner@aborted:
- {bat-adlm-1}: NOTRUN -> [FAIL][6]
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/bat-adlm-1/igt@runner@aborted.html
- {bat-adlp-6}: NOTRUN -> [FAIL][7]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/bat-adlp-6/igt@runner@aborted.html
Known issues
------------
Here are the changes found in Patchwork_107502v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_huc_copy@huc-copy:
- fi-rkl-11600: NOTRUN -> [SKIP][8] ([i915#2190])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/fi-rkl-11600/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@basic:
- fi-rkl-guc: NOTRUN -> [SKIP][9] ([i915#4613]) +3 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/fi-rkl-guc/igt@gem_lmem_swapping@basic.html
* igt@gem_lmem_swapping@parallel-random-engines:
- fi-rkl-11600: NOTRUN -> [SKIP][10] ([i915#4613]) +3 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/fi-rkl-11600/igt@gem_lmem_swapping@parallel-random-engines.html
* igt@gem_tiled_pread_basic:
- fi-rkl-11600: NOTRUN -> [SKIP][11] ([i915#3282])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/fi-rkl-11600/igt@gem_tiled_pread_basic.html
- fi-rkl-guc: NOTRUN -> [SKIP][12] ([i915#3282])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/fi-rkl-guc/igt@gem_tiled_pread_basic.html
* igt@i915_pm_backlight@basic-brightness:
- fi-rkl-guc: NOTRUN -> [SKIP][13] ([i915#3012])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/fi-rkl-guc/igt@i915_pm_backlight@basic-brightness.html
- fi-rkl-11600: NOTRUN -> [SKIP][14] ([i915#3012])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/fi-rkl-11600/igt@i915_pm_backlight@basic-brightness.html
* igt@i915_selftest@live@execlists:
- fi-bsw-kefka: [PASS][15] -> [INCOMPLETE][16] ([i915#5847])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12003/fi-bsw-kefka/igt@i915_selftest@live@execlists.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/fi-bsw-kefka/igt@i915_selftest@live@execlists.html
* igt@i915_selftest@live@gem:
- fi-pnv-d510: NOTRUN -> [DMESG-FAIL][17] ([i915#4528])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/fi-pnv-d510/igt@i915_selftest@live@gem.html
* igt@i915_suspend@basic-s3-without-i915:
- fi-rkl-11600: NOTRUN -> [INCOMPLETE][18] ([i915#5982])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/fi-rkl-11600/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_chamelium@hdmi-crc-fast:
- fi-rkl-guc: NOTRUN -> [SKIP][19] ([fdo#111827]) +8 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/fi-rkl-guc/igt@kms_chamelium@hdmi-crc-fast.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-rkl-11600: NOTRUN -> [SKIP][20] ([fdo#111827]) +7 similar issues
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/fi-rkl-11600/igt@kms_chamelium@hdmi-hpd-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor:
- fi-rkl-11600: NOTRUN -> [SKIP][21] ([i915#4103])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/fi-rkl-11600/igt@kms_cursor_legacy@basic-busy-flip-before-cursor.html
- fi-rkl-guc: NOTRUN -> [SKIP][22] ([i915#4103])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/fi-rkl-guc/igt@kms_cursor_legacy@basic-busy-flip-before-cursor.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-rkl-11600: NOTRUN -> [SKIP][23] ([fdo#109285] / [i915#4098])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/fi-rkl-11600/igt@kms_force_connector_basic@force-load-detect.html
- fi-rkl-guc: NOTRUN -> [SKIP][24] ([fdo#109285])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/fi-rkl-guc/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_psr@primary_mmap_gtt:
- fi-rkl-guc: NOTRUN -> [SKIP][25] ([i915#1072]) +3 similar issues
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/fi-rkl-guc/igt@kms_psr@primary_mmap_gtt.html
* igt@kms_psr@sprite_plane_onoff:
- fi-rkl-11600: NOTRUN -> [SKIP][26] ([i915#1072]) +3 similar issues
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/fi-rkl-11600/igt@kms_psr@sprite_plane_onoff.html
* igt@kms_setmode@basic-clone-single-crtc:
- fi-rkl-guc: NOTRUN -> [SKIP][27] ([i915#3555] / [i915#4098])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/fi-rkl-guc/igt@kms_setmode@basic-clone-single-crtc.html
- fi-rkl-11600: NOTRUN -> [SKIP][28] ([i915#3555] / [i915#4098])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/fi-rkl-11600/igt@kms_setmode@basic-clone-single-crtc.html
* igt@prime_vgem@basic-fence-read:
- fi-rkl-guc: NOTRUN -> [SKIP][29] ([fdo#109295] / [i915#3291] / [i915#3708]) +2 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/fi-rkl-guc/igt@prime_vgem@basic-fence-read.html
* igt@prime_vgem@basic-read:
- fi-rkl-11600: NOTRUN -> [SKIP][30] ([fdo#109295] / [i915#3291] / [i915#3708]) +2 similar issues
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/fi-rkl-11600/igt@prime_vgem@basic-read.html
* igt@prime_vgem@basic-userptr:
- fi-rkl-guc: NOTRUN -> [SKIP][31] ([fdo#109295] / [i915#3301] / [i915#3708])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/fi-rkl-guc/igt@prime_vgem@basic-userptr.html
- fi-rkl-11600: NOTRUN -> [SKIP][32] ([fdo#109295] / [i915#3301] / [i915#3708])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/fi-rkl-11600/igt@prime_vgem@basic-userptr.html
* igt@runner@aborted:
- fi-bsw-kefka: NOTRUN -> [FAIL][33] ([fdo#109271] / [i915#4312])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/fi-bsw-kefka/igt@runner@aborted.html
#### Possible fixes ####
* igt@core_auth@basic-auth:
- fi-rkl-guc: [TIMEOUT][34] -> [PASS][35] +3 similar issues
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12003/fi-rkl-guc/igt@core_auth@basic-auth.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/fi-rkl-guc/igt@core_auth@basic-auth.html
- {bat-dg2-9}: [TIMEOUT][36] -> [PASS][37] +1 similar issue
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12003/bat-dg2-9/igt@core_auth@basic-auth.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/bat-dg2-9/igt@core_auth@basic-auth.html
* igt@debugfs_test@read_all_entries:
- {bat-dg2-9}: [INCOMPLETE][38] -> [PASS][39]
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12003/bat-dg2-9/igt@debugfs_test@read_all_entries.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/bat-dg2-9/igt@debugfs_test@read_all_entries.html
* igt@i915_module_load@load:
- fi-rkl-guc: [TIMEOUT][40] ([i915#6627]) -> [PASS][41]
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12003/fi-rkl-guc/igt@i915_module_load@load.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/fi-rkl-guc/igt@i915_module_load@load.html
* igt@i915_selftest@live@requests:
- fi-pnv-d510: [DMESG-FAIL][42] ([i915#4528]) -> [PASS][43]
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12003/fi-pnv-d510/igt@i915_selftest@live@requests.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/fi-pnv-d510/igt@i915_selftest@live@requests.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#3003]: https://gitlab.freedesktop.org/drm/intel/issues/3003
[i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3595]: https://gitlab.freedesktop.org/drm/intel/issues/3595
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4817]: https://gitlab.freedesktop.org/drm/intel/issues/4817
[i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5847]: https://gitlab.freedesktop.org/drm/intel/issues/5847
[i915#5982]: https://gitlab.freedesktop.org/drm/intel/issues/5982
[i915#6011]: https://gitlab.freedesktop.org/drm/intel/issues/6011
[i915#6565]: https://gitlab.freedesktop.org/drm/intel/issues/6565
[i915#6627]: https://gitlab.freedesktop.org/drm/intel/issues/6627
Build changes
-------------
* Linux: CI_DRM_12003 -> Patchwork_107502v1
CI-20190529: 20190529
CI_DRM_12003: 5852b759ca0d67530d1dae6ab66c351e796fe39d @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6632: a0ac4d449e551fd5c78b56f85cd534330ea60507 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_107502v1: 5852b759ca0d67530d1dae6ab66c351e796fe39d @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
f96b72cf4b50 Revert "drm/i915/guc: Add delay to disable scheduling after pin count goes to zero"
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/index.html
[-- Attachment #2: Type: text/html, Size: 14728 bytes --]
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [Intel-gfx] [PATCH] Revert "drm/i915/guc: Add delay to disable scheduling after pin count goes to zero"
2022-08-19 12:39 [Intel-gfx] [PATCH] Revert "drm/i915/guc: Add delay to disable scheduling after pin count goes to zero" Matthew Auld
2022-08-19 13:25 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for " Patchwork
2022-08-19 13:48 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2022-08-19 15:46 ` John Harrison
2022-08-19 16:47 ` Teres Alexis, Alan Previn
2022-08-20 13:13 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for " Patchwork
3 siblings, 1 reply; 7+ messages in thread
From: John Harrison @ 2022-08-19 15:46 UTC (permalink / raw)
To: Matthew Auld, intel-gfx; +Cc: Alan Previn
On 8/19/2022 05:39, Matthew Auld wrote:
> This reverts commit 6a079903847cce1dd06345127d2a32f26d2cd9c6.
>
> Everything in CI using GuC is now timing out[1], and killing the machine
> with this change (perhaps a deadlock?). CI was recently on fire due to
> some changes coming in from -rc1, so likely the pre-merge CI results for
> this series were invalid? For now just revert, unless GuC experts
> already have a fix in mind.
>
> [1] https://intel-gfx-ci.01.org/tree/drm-tip/index.html?
>
> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> Cc: Matthew Brost <matthew.brost@intel.com>
> Cc: Alan Previn <alan.previn.teres.alexis@intel.com>
> Cc: John Harrison <John.C.Harrison@Intel.com>
Reviewed-by: John Harrison <John.C.Harrison@Intel.com>
Given that CI was claiming a pass for the original patch set, no we
don't have a fix in mind. It is most frustrating when CI says all green
if the entire universe is so broken that no tests were even running :(.
John.
> ---
> drivers/gpu/drm/i915/gem/i915_gem_context.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_context.h | 8 -
> drivers/gpu/drm/i915/gt/intel_context_types.h | 7 -
> drivers/gpu/drm/i915/gt/uc/intel_guc.h | 17 +-
> .../gpu/drm/i915/gt/uc/intel_guc_debugfs.c | 60 -------
> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 154 +++---------------
> drivers/gpu/drm/i915/i915_selftest.h | 2 -
> 7 files changed, 27 insertions(+), 223 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> index df7fd1b019ec..dabdfe09f5e5 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> @@ -1454,7 +1454,7 @@ static void engines_idle_release(struct i915_gem_context *ctx,
> int err;
>
> /* serialises with execbuf */
> - intel_context_close(ce);
> + set_bit(CONTEXT_CLOSED_BIT, &ce->flags);
> if (!intel_context_pin_if_active(ce))
> continue;
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_context.h b/drivers/gpu/drm/i915/gt/intel_context.h
> index f96420f0b5bb..8e2d70630c49 100644
> --- a/drivers/gpu/drm/i915/gt/intel_context.h
> +++ b/drivers/gpu/drm/i915/gt/intel_context.h
> @@ -276,14 +276,6 @@ static inline bool intel_context_is_barrier(const struct intel_context *ce)
> return test_bit(CONTEXT_BARRIER_BIT, &ce->flags);
> }
>
> -static inline void intel_context_close(struct intel_context *ce)
> -{
> - set_bit(CONTEXT_CLOSED_BIT, &ce->flags);
> -
> - if (ce->ops->close)
> - ce->ops->close(ce);
> -}
> -
> static inline bool intel_context_is_closed(const struct intel_context *ce)
> {
> return test_bit(CONTEXT_CLOSED_BIT, &ce->flags);
> diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h b/drivers/gpu/drm/i915/gt/intel_context_types.h
> index 86ac84e2edb9..04eacae1aca5 100644
> --- a/drivers/gpu/drm/i915/gt/intel_context_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
> @@ -43,8 +43,6 @@ struct intel_context_ops {
> void (*revoke)(struct intel_context *ce, struct i915_request *rq,
> unsigned int preempt_timeout_ms);
>
> - void (*close)(struct intel_context *ce);
> -
> int (*pre_pin)(struct intel_context *ce, struct i915_gem_ww_ctx *ww, void **vaddr);
> int (*pin)(struct intel_context *ce, void *vaddr);
> void (*unpin)(struct intel_context *ce);
> @@ -210,11 +208,6 @@ struct intel_context {
> * each priority bucket
> */
> u32 prio_count[GUC_CLIENT_PRIORITY_NUM];
> - /**
> - * @sched_disable_delay: worker to disable scheduling on this
> - * context
> - */
> - struct delayed_work sched_disable_delay;
> } guc_state;
>
> struct {
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> index 944b549b8797..804133df1ac9 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> @@ -112,10 +112,6 @@ struct intel_guc {
> * refs
> */
> struct list_head guc_id_list;
> - /**
> - * @guc_ids_in_use: Number single-lrc guc_ids in use
> - */
> - u16 guc_ids_in_use;
> /**
> * @destroyed_contexts: list of contexts waiting to be destroyed
> * (deregistered with the GuC)
> @@ -136,16 +132,6 @@ struct intel_guc {
> * @reset_fail_mask: mask of engines that failed to reset
> */
> intel_engine_mask_t reset_fail_mask;
> - /**
> - * @sched_disable_delay_ms: schedule disable delay, in ms, for
> - * contexts
> - */
> - u64 sched_disable_delay_ms;
> - /**
> - * @sched_disable_gucid_threshold: threshold of min remaining available
> - * guc_ids before we start bypassing the schedule disable delay
> - */
> - int sched_disable_gucid_threshold;
> } submission_state;
>
> /**
> @@ -475,10 +461,9 @@ void intel_guc_submission_reset_finish(struct intel_guc *guc);
> void intel_guc_submission_cancel_requests(struct intel_guc *guc);
>
> void intel_guc_load_status(struct intel_guc *guc, struct drm_printer *p);
> -void intel_guc_dump_time_info(struct intel_guc *guc, struct drm_printer *p);
>
> void intel_guc_write_barrier(struct intel_guc *guc);
>
> -int intel_guc_sched_disable_gucid_threshold_max(struct intel_guc *guc);
> +void intel_guc_dump_time_info(struct intel_guc *guc, struct drm_printer *p);
>
> #endif
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.c
> index c91b150bb7ac..25f09a420561 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.c
> @@ -71,72 +71,12 @@ static bool intel_eval_slpc_support(void *data)
> return intel_guc_slpc_is_used(guc);
> }
>
> -static int guc_sched_disable_delay_ms_get(void *data, u64 *val)
> -{
> - struct intel_guc *guc = data;
> -
> - if (!intel_guc_submission_is_used(guc))
> - return -ENODEV;
> -
> - *val = guc->submission_state.sched_disable_delay_ms;
> -
> - return 0;
> -}
> -
> -static int guc_sched_disable_delay_ms_set(void *data, u64 val)
> -{
> - struct intel_guc *guc = data;
> -
> - if (!intel_guc_submission_is_used(guc))
> - return -ENODEV;
> -
> - guc->submission_state.sched_disable_delay_ms = val;
> -
> - return 0;
> -}
> -DEFINE_SIMPLE_ATTRIBUTE(guc_sched_disable_delay_ms_fops,
> - guc_sched_disable_delay_ms_get,
> - guc_sched_disable_delay_ms_set, "%lld\n");
> -
> -static int guc_sched_disable_gucid_threshold_get(void *data, u64 *val)
> -{
> - struct intel_guc *guc = data;
> -
> - if (!intel_guc_submission_is_used(guc))
> - return -ENODEV;
> -
> - *val = guc->submission_state.sched_disable_gucid_threshold;
> - return 0;
> -}
> -
> -static int guc_sched_disable_gucid_threshold_set(void *data, u64 val)
> -{
> - struct intel_guc *guc = data;
> -
> - if (!intel_guc_submission_is_used(guc))
> - return -ENODEV;
> -
> - if (val > intel_guc_sched_disable_gucid_threshold_max(guc))
> - guc->submission_state.sched_disable_gucid_threshold =
> - intel_guc_sched_disable_gucid_threshold_max(guc);
> - else
> - guc->submission_state.sched_disable_gucid_threshold = val;
> -
> - return 0;
> -}
> -DEFINE_SIMPLE_ATTRIBUTE(guc_sched_disable_gucid_threshold_fops,
> - guc_sched_disable_gucid_threshold_get,
> - guc_sched_disable_gucid_threshold_set, "%lld\n");
> -
> void intel_guc_debugfs_register(struct intel_guc *guc, struct dentry *root)
> {
> static const struct intel_gt_debugfs_file files[] = {
> { "guc_info", &guc_info_fops, NULL },
> { "guc_registered_contexts", &guc_registered_contexts_fops, NULL },
> { "guc_slpc_info", &guc_slpc_info_fops, &intel_eval_slpc_support},
> - { "guc_sched_disable_delay_ms", &guc_sched_disable_delay_ms_fops, NULL },
> - { "guc_sched_disable_gucid_threshold", &guc_sched_disable_gucid_threshold_fops,
> - NULL },
> };
>
> if (!intel_guc_is_supported(guc))
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> index a0cebb4590e9..0d56b615bf78 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> @@ -65,13 +65,7 @@
> * corresponding G2H returns indicating the scheduling disable operation has
> * completed it is safe to unpin the context. While a disable is in flight it
> * isn't safe to resubmit the context so a fence is used to stall all future
> - * requests of that context until the G2H is returned. Because this interaction
> - * with the GuC takes a non-zero amount of time we delay the disabling of
> - * scheduling after the pin count goes to zero by a configurable period of time
> - * (see SCHED_DISABLE_DELAY_MS). The thought is this gives the user a window of
> - * time to resubmit something on the context before doing this costly operation.
> - * This delay is only done if the context isn't closed and the guc_id usage is
> - * less than a threshold (see NUM_SCHED_DISABLE_GUC_IDS_THRESHOLD).
> + * requests of that context until the G2H is returned.
> *
> * Context deregistration:
> * Before a context can be destroyed or if we steal its guc_id we must
> @@ -1995,9 +1989,6 @@ static int new_guc_id(struct intel_guc *guc, struct intel_context *ce)
> if (unlikely(ret < 0))
> return ret;
>
> - if (!intel_context_is_parent(ce))
> - ++guc->submission_state.guc_ids_in_use;
> -
> ce->guc_id.id = ret;
> return 0;
> }
> @@ -2007,16 +1998,14 @@ static void __release_guc_id(struct intel_guc *guc, struct intel_context *ce)
> GEM_BUG_ON(intel_context_is_child(ce));
>
> if (!context_guc_id_invalid(ce)) {
> - if (intel_context_is_parent(ce)) {
> + if (intel_context_is_parent(ce))
> bitmap_release_region(guc->submission_state.guc_ids_bitmap,
> ce->guc_id.id,
> order_base_2(ce->parallel.number_children
> + 1));
> - } else {
> - --guc->submission_state.guc_ids_in_use;
> + else
> ida_simple_remove(&guc->submission_state.guc_ids,
> ce->guc_id.id);
> - }
> clr_ctx_id_mapping(guc, ce->guc_id.id);
> set_context_guc_id_invalid(ce);
> }
> @@ -3004,98 +2993,41 @@ guc_context_revoke(struct intel_context *ce, struct i915_request *rq,
> }
> }
>
> -static void guc_context_sched_disable(struct intel_context *ce);
> -
> -static void do_sched_disable(struct intel_guc *guc, struct intel_context *ce,
> - unsigned long flags)
> - __releases(ce->guc_state.lock)
> +static void guc_context_sched_disable(struct intel_context *ce)
> {
> + struct intel_guc *guc = ce_to_guc(ce);
> + unsigned long flags;
> struct intel_runtime_pm *runtime_pm = &ce->engine->gt->i915->runtime_pm;
> intel_wakeref_t wakeref;
> + u16 guc_id;
>
> - lockdep_assert_held(&ce->guc_state.lock);
> -
> - spin_unlock_irqrestore(&ce->guc_state.lock, flags);
> -
> - with_intel_runtime_pm(runtime_pm, wakeref)
> - guc_context_sched_disable(ce);
> -}
> -
> -static bool bypass_sched_disable(struct intel_guc *guc,
> - struct intel_context *ce)
> -{
> - lockdep_assert_held(&ce->guc_state.lock);
> GEM_BUG_ON(intel_context_is_child(ce));
>
> - if (submission_disabled(guc) || context_guc_id_invalid(ce) ||
> - !ctx_id_mapped(guc, ce->guc_id.id)) {
> - clr_context_enabled(ce);
> - return true;
> - }
> -
> - return !context_enabled(ce);
> -}
> -
> -static void __delay_sched_disable(struct work_struct *wrk)
> -{
> - struct intel_context *ce =
> - container_of(wrk, typeof(*ce), guc_state.sched_disable_delay.work);
> - struct intel_guc *guc = ce_to_guc(ce);
> - unsigned long flags;
> -
> spin_lock_irqsave(&ce->guc_state.lock, flags);
>
> - if (bypass_sched_disable(guc, ce)) {
> - spin_unlock_irqrestore(&ce->guc_state.lock, flags);
> - intel_context_sched_disable_unpin(ce);
> - } else {
> - do_sched_disable(guc, ce, flags);
> - }
> -}
> -
> -static bool guc_id_pressure(struct intel_guc *guc, struct intel_context *ce)
> -{
> - /*
> - * parent contexts are perma-pinned, if we are unpinning do schedule
> - * disable immediately.
> - */
> - if (intel_context_is_parent(ce))
> - return true;
> -
> /*
> - * If we are beyond the threshold for avail guc_ids, do schedule disable immediately.
> + * We have to check if the context has been disabled by another thread,
> + * check if submssion has been disabled to seal a race with reset and
> + * finally check if any more requests have been committed to the
> + * context ensursing that a request doesn't slip through the
> + * 'context_pending_disable' fence.
> */
> - return guc->submission_state.guc_ids_in_use >
> - guc->submission_state.sched_disable_gucid_threshold;
> -}
> -
> -static void guc_context_sched_disable(struct intel_context *ce)
> -{
> - struct intel_guc *guc = ce_to_guc(ce);
> - u64 delay = guc->submission_state.sched_disable_delay_ms;
> - unsigned long flags;
> -
> - spin_lock_irqsave(&ce->guc_state.lock, flags);
> -
> - if (bypass_sched_disable(guc, ce)) {
> - spin_unlock_irqrestore(&ce->guc_state.lock, flags);
> - intel_context_sched_disable_unpin(ce);
> - } else if (!intel_context_is_closed(ce) && !guc_id_pressure(guc, ce) &&
> - delay) {
> + if (unlikely(!context_enabled(ce) || submission_disabled(guc) ||
> + context_has_committed_requests(ce))) {
> + clr_context_enabled(ce);
> spin_unlock_irqrestore(&ce->guc_state.lock, flags);
> - mod_delayed_work(system_unbound_wq,
> - &ce->guc_state.sched_disable_delay,
> - msecs_to_jiffies(delay));
> - } else {
> - do_sched_disable(guc, ce, flags);
> + goto unpin;
> }
> -}
> + guc_id = prep_context_pending_disable(ce);
>
> -static void guc_context_close(struct intel_context *ce)
> -{
> - if (test_bit(CONTEXT_GUC_INIT, &ce->flags) &&
> - cancel_delayed_work(&ce->guc_state.sched_disable_delay))
> - __delay_sched_disable(&ce->guc_state.sched_disable_delay.work);
> + spin_unlock_irqrestore(&ce->guc_state.lock, flags);
> +
> + with_intel_runtime_pm(runtime_pm, wakeref)
> + __guc_context_sched_disable(guc, ce, guc_id);
> +
> + return;
> +unpin:
> + intel_context_sched_disable_unpin(ce);
> }
>
> static inline void guc_lrc_desc_unpin(struct intel_context *ce)
> @@ -3414,8 +3346,6 @@ static void remove_from_context(struct i915_request *rq)
> static const struct intel_context_ops guc_context_ops = {
> .alloc = guc_context_alloc,
>
> - .close = guc_context_close,
> -
> .pre_pin = guc_context_pre_pin,
> .pin = guc_context_pin,
> .unpin = guc_context_unpin,
> @@ -3498,10 +3428,6 @@ static void guc_context_init(struct intel_context *ce)
> rcu_read_unlock();
>
> ce->guc_state.prio = map_i915_prio_to_guc_prio(prio);
> -
> - INIT_DELAYED_WORK(&ce->guc_state.sched_disable_delay,
> - __delay_sched_disable);
> -
> set_bit(CONTEXT_GUC_INIT, &ce->flags);
> }
>
> @@ -3539,9 +3465,6 @@ static int guc_request_alloc(struct i915_request *rq)
> if (unlikely(!test_bit(CONTEXT_GUC_INIT, &ce->flags)))
> guc_context_init(ce);
>
> - if (cancel_delayed_work(&ce->guc_state.sched_disable_delay))
> - intel_context_sched_disable_unpin(ce);
> -
> /*
> * Call pin_guc_id here rather than in the pinning step as with
> * dma_resv, contexts can be repeatedly pinned / unpinned trashing the
> @@ -3672,8 +3595,6 @@ static int guc_virtual_context_alloc(struct intel_context *ce)
> static const struct intel_context_ops virtual_guc_context_ops = {
> .alloc = guc_virtual_context_alloc,
>
> - .close = guc_context_close,
> -
> .pre_pin = guc_virtual_context_pre_pin,
> .pin = guc_virtual_context_pin,
> .unpin = guc_virtual_context_unpin,
> @@ -3763,8 +3684,6 @@ static void guc_child_context_destroy(struct kref *kref)
> static const struct intel_context_ops virtual_parent_context_ops = {
> .alloc = guc_virtual_context_alloc,
>
> - .close = guc_context_close,
> -
> .pre_pin = guc_context_pre_pin,
> .pin = guc_parent_context_pin,
> .unpin = guc_parent_context_unpin,
> @@ -4295,26 +4214,6 @@ static bool __guc_submission_selected(struct intel_guc *guc)
> return i915->params.enable_guc & ENABLE_GUC_SUBMISSION;
> }
>
> -int intel_guc_sched_disable_gucid_threshold_max(struct intel_guc *guc)
> -{
> - return guc->submission_state.num_guc_ids - NUMBER_MULTI_LRC_GUC_ID(guc);
> -}
> -
> -/*
> - * This default value of 33 milisecs (+1 milisec round up) ensures 30fps or higher
> - * workloads are able to enjoy the latency reduction when delaying the schedule-disable
> - * operation. This matches the 30fps game-render + encode (real world) workload this
> - * knob was tested against.
> - */
> -#define SCHED_DISABLE_DELAY_MS 34
> -
> -/*
> - * A threshold of 75% is a reasonable starting point considering that real world apps
> - * generally don't get anywhere near this.
> - */
> -#define NUM_SCHED_DISABLE_GUCIDS_DEFAULT_THRESHOLD(__guc) \
> - (((intel_guc_sched_disable_gucid_threshold_max(guc)) * 3) / 4)
> -
> void intel_guc_submission_init_early(struct intel_guc *guc)
> {
> xa_init_flags(&guc->context_lookup, XA_FLAGS_LOCK_IRQ);
> @@ -4331,10 +4230,7 @@ void intel_guc_submission_init_early(struct intel_guc *guc)
> spin_lock_init(&guc->timestamp.lock);
> INIT_DELAYED_WORK(&guc->timestamp.work, guc_timestamp_ping);
>
> - guc->submission_state.sched_disable_delay_ms = SCHED_DISABLE_DELAY_MS;
> guc->submission_state.num_guc_ids = GUC_MAX_CONTEXT_ID;
> - guc->submission_state.sched_disable_gucid_threshold =
> - NUM_SCHED_DISABLE_GUCIDS_DEFAULT_THRESHOLD(guc);
> guc->submission_supported = __guc_submission_supported(guc);
> guc->submission_selected = __guc_submission_selected(guc);
> }
> diff --git a/drivers/gpu/drm/i915/i915_selftest.h b/drivers/gpu/drm/i915/i915_selftest.h
> index bdf3e22c0a34..f54de0499be7 100644
> --- a/drivers/gpu/drm/i915/i915_selftest.h
> +++ b/drivers/gpu/drm/i915/i915_selftest.h
> @@ -92,14 +92,12 @@ int __i915_subtests(const char *caller,
> T, ARRAY_SIZE(T), data)
> #define i915_live_subtests(T, data) ({ \
> typecheck(struct drm_i915_private *, data); \
> - (data)->gt[0]->uc.guc.submission_state.sched_disable_delay_ms = 0; \
> __i915_subtests(__func__, \
> __i915_live_setup, __i915_live_teardown, \
> T, ARRAY_SIZE(T), data); \
> })
> #define intel_gt_live_subtests(T, data) ({ \
> typecheck(struct intel_gt *, data); \
> - (data)->uc.guc.submission_state.sched_disable_delay_ms = 0; \
> __i915_subtests(__func__, \
> __intel_gt_live_setup, __intel_gt_live_teardown, \
> T, ARRAY_SIZE(T), data); \
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [Intel-gfx] [PATCH] Revert "drm/i915/guc: Add delay to disable scheduling after pin count goes to zero"
2022-08-19 15:46 ` [Intel-gfx] [PATCH] " John Harrison
@ 2022-08-19 16:47 ` Teres Alexis, Alan Previn
2022-09-01 15:49 ` Teres Alexis, Alan Previn
0 siblings, 1 reply; 7+ messages in thread
From: Teres Alexis, Alan Previn @ 2022-08-19 16:47 UTC (permalink / raw)
To: Harrison, John C, Auld, Matthew, intel-gfx@lists.freedesktop.org
Will look into this - apologies for the trouble Matt.
...alan
-----Original Message-----
From: Harrison, John C <john.c.harrison@intel.com>
Sent: Friday, August 19, 2022 8:46 AM
To: Auld, Matthew <matthew.auld@intel.com>; intel-gfx@lists.freedesktop.org
Cc: Brost, Matthew <matthew.brost@intel.com>; Teres Alexis, Alan Previn <alan.previn.teres.alexis@intel.com>
Subject: Re: [PATCH] Revert "drm/i915/guc: Add delay to disable scheduling after pin count goes to zero"
On 8/19/2022 05:39, Matthew Auld wrote:
> This reverts commit 6a079903847cce1dd06345127d2a32f26d2cd9c6.
>
> Everything in CI using GuC is now timing out[1], and killing the
> machine with this change (perhaps a deadlock?). CI was recently on
> fire due to some changes coming in from -rc1, so likely the pre-merge
> CI results for this series were invalid? For now just revert, unless
> GuC experts already have a fix in mind.
>
> [1] https://intel-gfx-ci.01.org/tree/drm-tip/index.html?
>
> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> Cc: Matthew Brost <matthew.brost@intel.com>
> Cc: Alan Previn <alan.previn.teres.alexis@intel.com>
> Cc: John Harrison <John.C.Harrison@Intel.com>
Reviewed-by: John Harrison <John.C.Harrison@Intel.com>
Given that CI was claiming a pass for the original patch set, no we don't have a fix in mind. It is most frustrating when CI says all green if the entire universe is so broken that no tests were even running :(.
John.
> ---
> drivers/gpu/drm/i915/gem/i915_gem_context.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_context.h | 8 -
> drivers/gpu/drm/i915/gt/intel_context_types.h | 7 -
> drivers/gpu/drm/i915/gt/uc/intel_guc.h | 17 +-
> .../gpu/drm/i915/gt/uc/intel_guc_debugfs.c | 60 -------
> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 154 +++---------------
> drivers/gpu/drm/i915/i915_selftest.h | 2 -
> 7 files changed, 27 insertions(+), 223 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> index df7fd1b019ec..dabdfe09f5e5 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> @@ -1454,7 +1454,7 @@ static void engines_idle_release(struct i915_gem_context *ctx,
> int err;
>
> /* serialises with execbuf */
> - intel_context_close(ce);
> + set_bit(CONTEXT_CLOSED_BIT, &ce->flags);
> if (!intel_context_pin_if_active(ce))
> continue;
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_context.h
> b/drivers/gpu/drm/i915/gt/intel_context.h
> index f96420f0b5bb..8e2d70630c49 100644
> --- a/drivers/gpu/drm/i915/gt/intel_context.h
> +++ b/drivers/gpu/drm/i915/gt/intel_context.h
> @@ -276,14 +276,6 @@ static inline bool intel_context_is_barrier(const struct intel_context *ce)
> return test_bit(CONTEXT_BARRIER_BIT, &ce->flags);
> }
>
> -static inline void intel_context_close(struct intel_context *ce) -{
> - set_bit(CONTEXT_CLOSED_BIT, &ce->flags);
> -
> - if (ce->ops->close)
> - ce->ops->close(ce);
> -}
> -
> static inline bool intel_context_is_closed(const struct intel_context *ce)
> {
> return test_bit(CONTEXT_CLOSED_BIT, &ce->flags); diff --git
> a/drivers/gpu/drm/i915/gt/intel_context_types.h
> b/drivers/gpu/drm/i915/gt/intel_context_types.h
> index 86ac84e2edb9..04eacae1aca5 100644
> --- a/drivers/gpu/drm/i915/gt/intel_context_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
> @@ -43,8 +43,6 @@ struct intel_context_ops {
> void (*revoke)(struct intel_context *ce, struct i915_request *rq,
> unsigned int preempt_timeout_ms);
>
> - void (*close)(struct intel_context *ce);
> -
> int (*pre_pin)(struct intel_context *ce, struct i915_gem_ww_ctx *ww, void **vaddr);
> int (*pin)(struct intel_context *ce, void *vaddr);
> void (*unpin)(struct intel_context *ce); @@ -210,11 +208,6 @@
> struct intel_context {
> * each priority bucket
> */
> u32 prio_count[GUC_CLIENT_PRIORITY_NUM];
> - /**
> - * @sched_disable_delay: worker to disable scheduling on this
> - * context
> - */
> - struct delayed_work sched_disable_delay;
> } guc_state;
>
> struct {
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> index 944b549b8797..804133df1ac9 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> @@ -112,10 +112,6 @@ struct intel_guc {
> * refs
> */
> struct list_head guc_id_list;
> - /**
> - * @guc_ids_in_use: Number single-lrc guc_ids in use
> - */
> - u16 guc_ids_in_use;
> /**
> * @destroyed_contexts: list of contexts waiting to be destroyed
> * (deregistered with the GuC)
> @@ -136,16 +132,6 @@ struct intel_guc {
> * @reset_fail_mask: mask of engines that failed to reset
> */
> intel_engine_mask_t reset_fail_mask;
> - /**
> - * @sched_disable_delay_ms: schedule disable delay, in ms, for
> - * contexts
> - */
> - u64 sched_disable_delay_ms;
> - /**
> - * @sched_disable_gucid_threshold: threshold of min remaining available
> - * guc_ids before we start bypassing the schedule disable delay
> - */
> - int sched_disable_gucid_threshold;
> } submission_state;
>
> /**
> @@ -475,10 +461,9 @@ void intel_guc_submission_reset_finish(struct intel_guc *guc);
> void intel_guc_submission_cancel_requests(struct intel_guc *guc);
>
> void intel_guc_load_status(struct intel_guc *guc, struct drm_printer
> *p); -void intel_guc_dump_time_info(struct intel_guc *guc, struct
> drm_printer *p);
>
> void intel_guc_write_barrier(struct intel_guc *guc);
>
> -int intel_guc_sched_disable_gucid_threshold_max(struct intel_guc
> *guc);
> +void intel_guc_dump_time_info(struct intel_guc *guc, struct
> +drm_printer *p);
>
> #endif
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.c
> index c91b150bb7ac..25f09a420561 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.c
> @@ -71,72 +71,12 @@ static bool intel_eval_slpc_support(void *data)
> return intel_guc_slpc_is_used(guc);
> }
>
> -static int guc_sched_disable_delay_ms_get(void *data, u64 *val) -{
> - struct intel_guc *guc = data;
> -
> - if (!intel_guc_submission_is_used(guc))
> - return -ENODEV;
> -
> - *val = guc->submission_state.sched_disable_delay_ms;
> -
> - return 0;
> -}
> -
> -static int guc_sched_disable_delay_ms_set(void *data, u64 val) -{
> - struct intel_guc *guc = data;
> -
> - if (!intel_guc_submission_is_used(guc))
> - return -ENODEV;
> -
> - guc->submission_state.sched_disable_delay_ms = val;
> -
> - return 0;
> -}
> -DEFINE_SIMPLE_ATTRIBUTE(guc_sched_disable_delay_ms_fops,
> - guc_sched_disable_delay_ms_get,
> - guc_sched_disable_delay_ms_set, "%lld\n");
> -
> -static int guc_sched_disable_gucid_threshold_get(void *data, u64
> *val) -{
> - struct intel_guc *guc = data;
> -
> - if (!intel_guc_submission_is_used(guc))
> - return -ENODEV;
> -
> - *val = guc->submission_state.sched_disable_gucid_threshold;
> - return 0;
> -}
> -
> -static int guc_sched_disable_gucid_threshold_set(void *data, u64 val)
> -{
> - struct intel_guc *guc = data;
> -
> - if (!intel_guc_submission_is_used(guc))
> - return -ENODEV;
> -
> - if (val > intel_guc_sched_disable_gucid_threshold_max(guc))
> - guc->submission_state.sched_disable_gucid_threshold =
> - intel_guc_sched_disable_gucid_threshold_max(guc);
> - else
> - guc->submission_state.sched_disable_gucid_threshold = val;
> -
> - return 0;
> -}
> -DEFINE_SIMPLE_ATTRIBUTE(guc_sched_disable_gucid_threshold_fops,
> - guc_sched_disable_gucid_threshold_get,
> - guc_sched_disable_gucid_threshold_set, "%lld\n");
> -
> void intel_guc_debugfs_register(struct intel_guc *guc, struct dentry *root)
> {
> static const struct intel_gt_debugfs_file files[] = {
> { "guc_info", &guc_info_fops, NULL },
> { "guc_registered_contexts", &guc_registered_contexts_fops, NULL },
> { "guc_slpc_info", &guc_slpc_info_fops, &intel_eval_slpc_support},
> - { "guc_sched_disable_delay_ms", &guc_sched_disable_delay_ms_fops, NULL },
> - { "guc_sched_disable_gucid_threshold", &guc_sched_disable_gucid_threshold_fops,
> - NULL },
> };
>
> if (!intel_guc_is_supported(guc))
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> index a0cebb4590e9..0d56b615bf78 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> @@ -65,13 +65,7 @@
> * corresponding G2H returns indicating the scheduling disable operation has
> * completed it is safe to unpin the context. While a disable is in flight it
> * isn't safe to resubmit the context so a fence is used to stall
> all future
> - * requests of that context until the G2H is returned. Because this
> interaction
> - * with the GuC takes a non-zero amount of time we delay the
> disabling of
> - * scheduling after the pin count goes to zero by a configurable
> period of time
> - * (see SCHED_DISABLE_DELAY_MS). The thought is this gives the user a
> window of
> - * time to resubmit something on the context before doing this costly operation.
> - * This delay is only done if the context isn't closed and the guc_id
> usage is
> - * less than a threshold (see NUM_SCHED_DISABLE_GUC_IDS_THRESHOLD).
> + * requests of that context until the G2H is returned.
> *
> * Context deregistration:
> * Before a context can be destroyed or if we steal its guc_id we
> must @@ -1995,9 +1989,6 @@ static int new_guc_id(struct intel_guc *guc, struct intel_context *ce)
> if (unlikely(ret < 0))
> return ret;
>
> - if (!intel_context_is_parent(ce))
> - ++guc->submission_state.guc_ids_in_use;
> -
> ce->guc_id.id = ret;
> return 0;
> }
> @@ -2007,16 +1998,14 @@ static void __release_guc_id(struct intel_guc *guc, struct intel_context *ce)
> GEM_BUG_ON(intel_context_is_child(ce));
>
> if (!context_guc_id_invalid(ce)) {
> - if (intel_context_is_parent(ce)) {
> + if (intel_context_is_parent(ce))
> bitmap_release_region(guc->submission_state.guc_ids_bitmap,
> ce->guc_id.id,
> order_base_2(ce->parallel.number_children
> + 1));
> - } else {
> - --guc->submission_state.guc_ids_in_use;
> + else
> ida_simple_remove(&guc->submission_state.guc_ids,
> ce->guc_id.id);
> - }
> clr_ctx_id_mapping(guc, ce->guc_id.id);
> set_context_guc_id_invalid(ce);
> }
> @@ -3004,98 +2993,41 @@ guc_context_revoke(struct intel_context *ce, struct i915_request *rq,
> }
> }
>
> -static void guc_context_sched_disable(struct intel_context *ce);
> -
> -static void do_sched_disable(struct intel_guc *guc, struct intel_context *ce,
> - unsigned long flags)
> - __releases(ce->guc_state.lock)
> +static void guc_context_sched_disable(struct intel_context *ce)
> {
> + struct intel_guc *guc = ce_to_guc(ce);
> + unsigned long flags;
> struct intel_runtime_pm *runtime_pm = &ce->engine->gt->i915->runtime_pm;
> intel_wakeref_t wakeref;
> + u16 guc_id;
>
> - lockdep_assert_held(&ce->guc_state.lock);
> -
> - spin_unlock_irqrestore(&ce->guc_state.lock, flags);
> -
> - with_intel_runtime_pm(runtime_pm, wakeref)
> - guc_context_sched_disable(ce);
> -}
> -
> -static bool bypass_sched_disable(struct intel_guc *guc,
> - struct intel_context *ce)
> -{
> - lockdep_assert_held(&ce->guc_state.lock);
> GEM_BUG_ON(intel_context_is_child(ce));
>
> - if (submission_disabled(guc) || context_guc_id_invalid(ce) ||
> - !ctx_id_mapped(guc, ce->guc_id.id)) {
> - clr_context_enabled(ce);
> - return true;
> - }
> -
> - return !context_enabled(ce);
> -}
> -
> -static void __delay_sched_disable(struct work_struct *wrk) -{
> - struct intel_context *ce =
> - container_of(wrk, typeof(*ce), guc_state.sched_disable_delay.work);
> - struct intel_guc *guc = ce_to_guc(ce);
> - unsigned long flags;
> -
> spin_lock_irqsave(&ce->guc_state.lock, flags);
>
> - if (bypass_sched_disable(guc, ce)) {
> - spin_unlock_irqrestore(&ce->guc_state.lock, flags);
> - intel_context_sched_disable_unpin(ce);
> - } else {
> - do_sched_disable(guc, ce, flags);
> - }
> -}
> -
> -static bool guc_id_pressure(struct intel_guc *guc, struct
> intel_context *ce) -{
> - /*
> - * parent contexts are perma-pinned, if we are unpinning do schedule
> - * disable immediately.
> - */
> - if (intel_context_is_parent(ce))
> - return true;
> -
> /*
> - * If we are beyond the threshold for avail guc_ids, do schedule disable immediately.
> + * We have to check if the context has been disabled by another thread,
> + * check if submssion has been disabled to seal a race with reset and
> + * finally check if any more requests have been committed to the
> + * context ensursing that a request doesn't slip through the
> + * 'context_pending_disable' fence.
> */
> - return guc->submission_state.guc_ids_in_use >
> - guc->submission_state.sched_disable_gucid_threshold;
> -}
> -
> -static void guc_context_sched_disable(struct intel_context *ce) -{
> - struct intel_guc *guc = ce_to_guc(ce);
> - u64 delay = guc->submission_state.sched_disable_delay_ms;
> - unsigned long flags;
> -
> - spin_lock_irqsave(&ce->guc_state.lock, flags);
> -
> - if (bypass_sched_disable(guc, ce)) {
> - spin_unlock_irqrestore(&ce->guc_state.lock, flags);
> - intel_context_sched_disable_unpin(ce);
> - } else if (!intel_context_is_closed(ce) && !guc_id_pressure(guc, ce) &&
> - delay) {
> + if (unlikely(!context_enabled(ce) || submission_disabled(guc) ||
> + context_has_committed_requests(ce))) {
> + clr_context_enabled(ce);
> spin_unlock_irqrestore(&ce->guc_state.lock, flags);
> - mod_delayed_work(system_unbound_wq,
> - &ce->guc_state.sched_disable_delay,
> - msecs_to_jiffies(delay));
> - } else {
> - do_sched_disable(guc, ce, flags);
> + goto unpin;
> }
> -}
> + guc_id = prep_context_pending_disable(ce);
>
> -static void guc_context_close(struct intel_context *ce) -{
> - if (test_bit(CONTEXT_GUC_INIT, &ce->flags) &&
> - cancel_delayed_work(&ce->guc_state.sched_disable_delay))
> - __delay_sched_disable(&ce->guc_state.sched_disable_delay.work);
> + spin_unlock_irqrestore(&ce->guc_state.lock, flags);
> +
> + with_intel_runtime_pm(runtime_pm, wakeref)
> + __guc_context_sched_disable(guc, ce, guc_id);
> +
> + return;
> +unpin:
> + intel_context_sched_disable_unpin(ce);
> }
>
> static inline void guc_lrc_desc_unpin(struct intel_context *ce) @@
> -3414,8 +3346,6 @@ static void remove_from_context(struct i915_request *rq)
> static const struct intel_context_ops guc_context_ops = {
> .alloc = guc_context_alloc,
>
> - .close = guc_context_close,
> -
> .pre_pin = guc_context_pre_pin,
> .pin = guc_context_pin,
> .unpin = guc_context_unpin,
> @@ -3498,10 +3428,6 @@ static void guc_context_init(struct intel_context *ce)
> rcu_read_unlock();
>
> ce->guc_state.prio = map_i915_prio_to_guc_prio(prio);
> -
> - INIT_DELAYED_WORK(&ce->guc_state.sched_disable_delay,
> - __delay_sched_disable);
> -
> set_bit(CONTEXT_GUC_INIT, &ce->flags);
> }
>
> @@ -3539,9 +3465,6 @@ static int guc_request_alloc(struct i915_request *rq)
> if (unlikely(!test_bit(CONTEXT_GUC_INIT, &ce->flags)))
> guc_context_init(ce);
>
> - if (cancel_delayed_work(&ce->guc_state.sched_disable_delay))
> - intel_context_sched_disable_unpin(ce);
> -
> /*
> * Call pin_guc_id here rather than in the pinning step as with
> * dma_resv, contexts can be repeatedly pinned / unpinned trashing
> the @@ -3672,8 +3595,6 @@ static int guc_virtual_context_alloc(struct intel_context *ce)
> static const struct intel_context_ops virtual_guc_context_ops = {
> .alloc = guc_virtual_context_alloc,
>
> - .close = guc_context_close,
> -
> .pre_pin = guc_virtual_context_pre_pin,
> .pin = guc_virtual_context_pin,
> .unpin = guc_virtual_context_unpin, @@ -3763,8 +3684,6 @@ static
> void guc_child_context_destroy(struct kref *kref)
> static const struct intel_context_ops virtual_parent_context_ops = {
> .alloc = guc_virtual_context_alloc,
>
> - .close = guc_context_close,
> -
> .pre_pin = guc_context_pre_pin,
> .pin = guc_parent_context_pin,
> .unpin = guc_parent_context_unpin,
> @@ -4295,26 +4214,6 @@ static bool __guc_submission_selected(struct intel_guc *guc)
> return i915->params.enable_guc & ENABLE_GUC_SUBMISSION;
> }
>
> -int intel_guc_sched_disable_gucid_threshold_max(struct intel_guc
> *guc) -{
> - return guc->submission_state.num_guc_ids - NUMBER_MULTI_LRC_GUC_ID(guc);
> -}
> -
> -/*
> - * This default value of 33 milisecs (+1 milisec round up) ensures
> 30fps or higher
> - * workloads are able to enjoy the latency reduction when delaying
> the schedule-disable
> - * operation. This matches the 30fps game-render + encode (real
> world) workload this
> - * knob was tested against.
> - */
> -#define SCHED_DISABLE_DELAY_MS 34
> -
> -/*
> - * A threshold of 75% is a reasonable starting point considering that
> real world apps
> - * generally don't get anywhere near this.
> - */
> -#define NUM_SCHED_DISABLE_GUCIDS_DEFAULT_THRESHOLD(__guc) \
> - (((intel_guc_sched_disable_gucid_threshold_max(guc)) * 3) / 4)
> -
> void intel_guc_submission_init_early(struct intel_guc *guc)
> {
> xa_init_flags(&guc->context_lookup, XA_FLAGS_LOCK_IRQ); @@ -4331,10
> +4230,7 @@ void intel_guc_submission_init_early(struct intel_guc *guc)
> spin_lock_init(&guc->timestamp.lock);
> INIT_DELAYED_WORK(&guc->timestamp.work, guc_timestamp_ping);
>
> - guc->submission_state.sched_disable_delay_ms = SCHED_DISABLE_DELAY_MS;
> guc->submission_state.num_guc_ids = GUC_MAX_CONTEXT_ID;
> - guc->submission_state.sched_disable_gucid_threshold =
> - NUM_SCHED_DISABLE_GUCIDS_DEFAULT_THRESHOLD(guc);
> guc->submission_supported = __guc_submission_supported(guc);
> guc->submission_selected = __guc_submission_selected(guc);
> }
> diff --git a/drivers/gpu/drm/i915/i915_selftest.h
> b/drivers/gpu/drm/i915/i915_selftest.h
> index bdf3e22c0a34..f54de0499be7 100644
> --- a/drivers/gpu/drm/i915/i915_selftest.h
> +++ b/drivers/gpu/drm/i915/i915_selftest.h
> @@ -92,14 +92,12 @@ int __i915_subtests(const char *caller,
> T, ARRAY_SIZE(T), data)
> #define i915_live_subtests(T, data) ({ \
> typecheck(struct drm_i915_private *, data); \
> - (data)->gt[0]->uc.guc.submission_state.sched_disable_delay_ms = 0; \
> __i915_subtests(__func__, \
> __i915_live_setup, __i915_live_teardown, \
> T, ARRAY_SIZE(T), data); \
> })
> #define intel_gt_live_subtests(T, data) ({ \
> typecheck(struct intel_gt *, data); \
> - (data)->uc.guc.submission_state.sched_disable_delay_ms = 0; \
> __i915_subtests(__func__, \
> __intel_gt_live_setup, __intel_gt_live_teardown, \
> T, ARRAY_SIZE(T), data); \
^ permalink raw reply [flat|nested] 7+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for Revert "drm/i915/guc: Add delay to disable scheduling after pin count goes to zero"
2022-08-19 12:39 [Intel-gfx] [PATCH] Revert "drm/i915/guc: Add delay to disable scheduling after pin count goes to zero" Matthew Auld
` (2 preceding siblings ...)
2022-08-19 15:46 ` [Intel-gfx] [PATCH] " John Harrison
@ 2022-08-20 13:13 ` Patchwork
3 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2022-08-20 13:13 UTC (permalink / raw)
To: Matthew Auld; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 34851 bytes --]
== Series Details ==
Series: Revert "drm/i915/guc: Add delay to disable scheduling after pin count goes to zero"
URL : https://patchwork.freedesktop.org/series/107502/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12003_full -> Patchwork_107502v1_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_107502v1_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_107502v1_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (10 -> 13)
------------------------------
Additional (3): shard-rkl shard-dg1 shard-tglu
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_107502v1_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_flip@flip-vs-blocking-wf-vblank@d-edp1:
- shard-tglb: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12003/shard-tglb3/igt@kms_flip@flip-vs-blocking-wf-vblank@d-edp1.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/shard-tglb7/igt@kms_flip@flip-vs-blocking-wf-vblank@d-edp1.html
Known issues
------------
Here are the changes found in Patchwork_107502v1_full that come from known issues:
### CI changes ###
#### Issues hit ####
* boot:
- shard-snb: ([PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26], [PASS][27]) -> ([PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [FAIL][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50], [PASS][51], [PASS][52]) ([i915#4338])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12003/shard-snb6/boot.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12003/shard-snb6/boot.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12003/shard-snb6/boot.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12003/shard-snb6/boot.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12003/shard-snb6/boot.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12003/shard-snb6/boot.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12003/shard-snb5/boot.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12003/shard-snb5/boot.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12003/shard-snb5/boot.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12003/shard-snb5/boot.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12003/shard-snb5/boot.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12003/shard-snb5/boot.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12003/shard-snb4/boot.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12003/shard-snb4/boot.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12003/shard-snb4/boot.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12003/shard-snb4/boot.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12003/shard-snb4/boot.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12003/shard-snb4/boot.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12003/shard-snb4/boot.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12003/shard-snb2/boot.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12003/shard-snb2/boot.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12003/shard-snb2/boot.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12003/shard-snb2/boot.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12003/shard-snb2/boot.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12003/shard-snb2/boot.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/shard-snb6/boot.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/shard-snb6/boot.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/shard-snb6/boot.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/shard-snb6/boot.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/shard-snb6/boot.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/shard-snb6/boot.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/shard-snb5/boot.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/shard-snb5/boot.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/shard-snb5/boot.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/shard-snb5/boot.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/shard-snb5/boot.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/shard-snb5/boot.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/shard-snb5/boot.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/shard-snb4/boot.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/shard-snb4/boot.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/shard-snb4/boot.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/shard-snb4/boot.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/shard-snb4/boot.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/shard-snb4/boot.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/shard-snb4/boot.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/shard-snb2/boot.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/shard-snb2/boot.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/shard-snb2/boot.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/shard-snb2/boot.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/shard-snb2/boot.html
### IGT changes ###
#### Issues hit ####
* igt@gem_eio@unwedge-stress:
- shard-tglb: [PASS][53] -> [FAIL][54] ([i915#5784])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12003/shard-tglb7/igt@gem_eio@unwedge-stress.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/shard-tglb5/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_balancer@parallel-contexts:
- shard-iclb: [PASS][55] -> [SKIP][56] ([i915#4525]) +1 similar issue
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12003/shard-iclb4/igt@gem_exec_balancer@parallel-contexts.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/shard-iclb8/igt@gem_exec_balancer@parallel-contexts.html
* igt@gem_exec_endless@dispatch@vcs0:
- shard-tglb: [PASS][57] -> [INCOMPLETE][58] ([i915#3778])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12003/shard-tglb7/igt@gem_exec_endless@dispatch@vcs0.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/shard-tglb7/igt@gem_exec_endless@dispatch@vcs0.html
* igt@gem_exec_fair@basic-deadline:
- shard-kbl: [PASS][59] -> [FAIL][60] ([i915#2846])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12003/shard-kbl7/igt@gem_exec_fair@basic-deadline.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/shard-kbl1/igt@gem_exec_fair@basic-deadline.html
- shard-glk: NOTRUN -> [FAIL][61] ([i915#2846])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/shard-glk8/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-glk: [PASS][62] -> [FAIL][63] ([i915#2842])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12003/shard-glk3/igt@gem_exec_fair@basic-none-share@rcs0.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/shard-glk3/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-apl: [PASS][64] -> [FAIL][65] ([i915#2842])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12003/shard-apl6/igt@gem_exec_fair@basic-none-solo@rcs0.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/shard-apl3/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [PASS][66] -> [FAIL][67] ([i915#2842])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12003/shard-tglb7/igt@gem_exec_fair@basic-pace-share@rcs0.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/shard-tglb5/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-kbl: [PASS][68] -> [FAIL][69] ([i915#2842])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12003/shard-kbl4/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/shard-kbl1/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [PASS][70] -> [FAIL][71] ([i915#2842])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12003/shard-iclb5/igt@gem_exec_fair@basic-throttle@rcs0.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/shard-iclb7/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_userptr_blits@vma-merge:
- shard-glk: NOTRUN -> [FAIL][72] ([i915#3318])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/shard-glk8/igt@gem_userptr_blits@vma-merge.html
* igt@i915_pm_dc@dc6-psr:
- shard-iclb: [PASS][73] -> [FAIL][74] ([i915#454])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12003/shard-iclb1/igt@i915_pm_dc@dc6-psr.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/shard-iclb6/igt@i915_pm_dc@dc6-psr.html
* igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
- shard-kbl: NOTRUN -> [SKIP][75] ([fdo#109271] / [i915#3886]) +5 similar issues
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/shard-kbl1/igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_mc_ccs:
- shard-glk: NOTRUN -> [SKIP][76] ([fdo#109271] / [i915#3886]) +5 similar issues
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/shard-glk8/igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
- shard-apl: NOTRUN -> [SKIP][77] ([fdo#109271] / [i915#3886]) +4 similar issues
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/shard-apl1/igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-d-bad-pixel-format-4_tiled_dg2_mc_ccs:
- shard-kbl: NOTRUN -> [SKIP][78] ([fdo#109271]) +91 similar issues
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/shard-kbl1/igt@kms_ccs@pipe-d-bad-pixel-format-4_tiled_dg2_mc_ccs.html
* igt@kms_ccs@pipe-d-ccs-on-another-bo-yf_tiled_ccs:
- shard-glk: NOTRUN -> [SKIP][79] ([fdo#109271]) +51 similar issues
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/shard-glk9/igt@kms_ccs@pipe-d-ccs-on-another-bo-yf_tiled_ccs.html
* igt@kms_chamelium@dp-hpd-storm:
- shard-kbl: NOTRUN -> [SKIP][80] ([fdo#109271] / [fdo#111827]) +7 similar issues
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/shard-kbl1/igt@kms_chamelium@dp-hpd-storm.html
* igt@kms_chamelium@hdmi-frame-dump:
- shard-apl: NOTRUN -> [SKIP][81] ([fdo#109271] / [fdo#111827]) +2 similar issues
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/shard-apl1/igt@kms_chamelium@hdmi-frame-dump.html
- shard-glk: NOTRUN -> [SKIP][82] ([fdo#109271] / [fdo#111827]) +4 similar issues
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/shard-glk9/igt@kms_chamelium@hdmi-frame-dump.html
* igt@kms_flip@flip-vs-suspend-interruptible@c-dp1:
- shard-kbl: [PASS][83] -> [DMESG-WARN][84] ([i915#180]) +4 similar issues
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12003/shard-kbl1/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/shard-kbl4/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling@pipe-a-valid-mode:
- shard-iclb: NOTRUN -> [SKIP][85] ([i915#2672]) +6 similar issues
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/shard-iclb7/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling@pipe-a-valid-mode.html
* igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-cpu:
- shard-apl: NOTRUN -> [SKIP][86] ([fdo#109271]) +32 similar issues
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/shard-apl1/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-cpu.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb:
- shard-glk: NOTRUN -> [FAIL][87] ([fdo#108145] / [i915#265])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/shard-glk9/igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb.html
- shard-apl: NOTRUN -> [FAIL][88] ([fdo#108145] / [i915#265])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/shard-apl1/igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max:
- shard-kbl: NOTRUN -> [FAIL][89] ([fdo#108145] / [i915#265])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/shard-kbl1/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb:
- shard-apl: NOTRUN -> [FAIL][90] ([i915#265])
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/shard-apl1/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html
- shard-glk: NOTRUN -> [FAIL][91] ([i915#265])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/shard-glk9/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-b-edp-1:
- shard-iclb: [PASS][92] -> [SKIP][93] ([i915#5235]) +2 similar issues
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12003/shard-iclb8/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-b-edp-1.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/shard-iclb2/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-b-edp-1.html
* igt@kms_psr2_sf@overlay-plane-move-continuous-sf:
- shard-apl: NOTRUN -> [SKIP][94] ([fdo#109271] / [i915#658]) +1 similar issue
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/shard-apl1/igt@kms_psr2_sf@overlay-plane-move-continuous-sf.html
* igt@kms_psr2_sf@plane-move-sf-dmg-area:
- shard-kbl: NOTRUN -> [SKIP][95] ([fdo#109271] / [i915#658])
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/shard-kbl1/igt@kms_psr2_sf@plane-move-sf-dmg-area.html
* igt@kms_psr2_su@frontbuffer-xrgb8888:
- shard-glk: NOTRUN -> [SKIP][96] ([fdo#109271] / [i915#658]) +2 similar issues
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/shard-glk9/igt@kms_psr2_su@frontbuffer-xrgb8888.html
* igt@kms_vblank@pipe-b-ts-continuation-suspend:
- shard-glk: NOTRUN -> [INCOMPLETE][97] ([i915#6598])
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/shard-glk8/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
* igt@sysfs_clients@split-50:
- shard-kbl: NOTRUN -> [SKIP][98] ([fdo#109271] / [i915#2994])
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/shard-kbl1/igt@sysfs_clients@split-50.html
#### Possible fixes ####
* igt@gem_eio@unwedge-stress:
- shard-iclb: [TIMEOUT][99] ([i915#3070]) -> [PASS][100]
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12003/shard-iclb5/igt@gem_eio@unwedge-stress.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/shard-iclb7/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_balancer@parallel-balancer:
- shard-iclb: [SKIP][101] ([i915#4525]) -> [PASS][102]
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12003/shard-iclb6/igt@gem_exec_balancer@parallel-balancer.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/shard-iclb1/igt@gem_exec_balancer@parallel-balancer.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [FAIL][103] ([i915#2842]) -> [PASS][104]
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12003/shard-glk9/igt@gem_exec_fair@basic-pace-share@rcs0.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/shard-glk2/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-iclb: [FAIL][105] ([i915#2842]) -> [PASS][106]
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12003/shard-iclb8/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/shard-iclb2/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-kbl: [FAIL][107] ([i915#2842]) -> [PASS][108]
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12003/shard-kbl1/igt@gem_exec_fair@basic-pace@vcs1.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/shard-kbl4/igt@gem_exec_fair@basic-pace@vcs1.html
* igt@gem_workarounds@suspend-resume-fd:
- shard-kbl: [DMESG-WARN][109] ([i915#180]) -> [PASS][110] +7 similar issues
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12003/shard-kbl4/igt@gem_workarounds@suspend-resume-fd.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/shard-kbl1/igt@gem_workarounds@suspend-resume-fd.html
* igt@gen9_exec_parse@allowed-all:
- shard-glk: [DMESG-WARN][111] ([i915#5566] / [i915#716]) -> [PASS][112] +1 similar issue
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12003/shard-glk6/igt@gen9_exec_parse@allowed-all.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/shard-glk8/igt@gen9_exec_parse@allowed-all.html
* igt@gen9_exec_parse@allowed-single:
- shard-apl: [DMESG-WARN][113] ([i915#5566] / [i915#716]) -> [PASS][114]
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12003/shard-apl1/igt@gen9_exec_parse@allowed-single.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/shard-apl1/igt@gen9_exec_parse@allowed-single.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a2:
- shard-glk: [FAIL][115] ([i915#79]) -> [PASS][116]
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12003/shard-glk7/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a2.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/shard-glk5/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a2.html
* igt@kms_hdr@bpc-switch-dpms@pipe-a-dp-1:
- shard-kbl: [FAIL][117] ([i915#1188]) -> [PASS][118] +1 similar issue
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12003/shard-kbl4/igt@kms_hdr@bpc-switch-dpms@pipe-a-dp-1.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/shard-kbl7/igt@kms_hdr@bpc-switch-dpms@pipe-a-dp-1.html
* igt@kms_vblank@pipe-c-ts-continuation-suspend:
- shard-kbl: [INCOMPLETE][119] ([i915#4939]) -> [PASS][120]
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12003/shard-kbl4/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/shard-kbl1/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
#### Warnings ####
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-kbl: [SKIP][121] ([fdo#109271]) -> [FAIL][122] ([i915#2842])
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12003/shard-kbl1/igt@gem_exec_fair@basic-pace@rcs0.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/shard-kbl4/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@kms_flip@flip-vs-suspend@a-dp1:
- shard-apl: [INCOMPLETE][123] ([i915#6598]) -> [INCOMPLETE][124] ([i915#1982] / [i915#6598])
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12003/shard-apl7/igt@kms_flip@flip-vs-suspend@a-dp1.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/shard-apl8/igt@kms_flip@flip-vs-suspend@a-dp1.html
* igt@runner@aborted:
- shard-apl: ([FAIL][125], [FAIL][126]) ([fdo#109271] / [i915#3002] / [i915#4312] / [i915#5257] / [i915#6599]) -> [FAIL][127] ([i915#3002] / [i915#4312] / [i915#5257] / [i915#6599])
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12003/shard-apl1/igt@runner@aborted.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12003/shard-apl8/igt@runner@aborted.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/shard-apl8/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302
[fdo#109303]: https://bugs.freedesktop.org/show_bug.cgi?id=109303
[fdo#109307]: https://bugs.freedesktop.org/show_bug.cgi?id=109307
[fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
[fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
[fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312
[fdo#109313]: https://bugs.freedesktop.org/show_bug.cgi?id=109313
[fdo#109314]: https://bugs.freedesktop.org/show_bug.cgi?id=109314
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110542]: https://bugs.freedesktop.org/show_bug.cgi?id=110542
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111314]: https://bugs.freedesktop.org/show_bug.cgi?id=111314
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111644]: https://bugs.freedesktop.org/show_bug.cgi?id=111644
[fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
[fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
[i915#1063]: https://gitlab.freedesktop.org/drm/intel/issues/1063
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#1257]: https://gitlab.freedesktop.org/drm/intel/issues/1257
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1755]: https://gitlab.freedesktop.org/drm/intel/issues/1755
[i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#1902]: https://gitlab.freedesktop.org/drm/intel/issues/1902
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2410]: https://gitlab.freedesktop.org/drm/intel/issues/2410
[i915#2433]: https://gitlab.freedesktop.org/drm/intel/issues/2433
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2530]: https://gitlab.freedesktop.org/drm/intel/issues/2530
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#284]: https://gitlab.freedesktop.org/drm/intel/issues/284
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
[i915#3070]: https://gitlab.freedesktop.org/drm/intel/issues/3070
[i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
[i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
[i915#3323]: https://gitlab.freedesktop.org/drm/intel/issues/3323
[i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469
[i915#3528]: https://gitlab.freedesktop.org/drm/intel/issues/3528
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
[i915#3778]: https://gitlab.freedesktop.org/drm/intel/issues/3778
[i915#3804]: https://gitlab.freedesktop.org/drm/intel/issues/3804
[i915#3826]: https://gitlab.freedesktop.org/drm/intel/issues/3826
[i915#3828]: https://gitlab.freedesktop.org/drm/intel/issues/3828
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3936]: https://gitlab.freedesktop.org/drm/intel/issues/3936
[i915#3952]: https://gitlab.freedesktop.org/drm/intel/issues/3952
[i915#3966]: https://gitlab.freedesktop.org/drm/intel/issues/3966
[i915#4016]: https://gitlab.freedesktop.org/drm/intel/issues/4016
[i915#4032]: https://gitlab.freedesktop.org/drm/intel/issues/4032
[i915#4036]: https://gitlab.freedesktop.org/drm/intel/issues/4036
[i915#404]: https://gitlab.freedesktop.org/drm/intel/issues/404
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
[i915#426]: https://gitlab.freedesktop.org/drm/intel/issues/426
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#433]: https://gitlab.freedesktop.org/drm/intel/issues/433
[i915#4338]: https://gitlab.freedesktop.org/drm/intel/issues/4338
[i915#4369]: https://gitlab.freedesktop.org/drm/intel/issues/4369
[i915#4387]: https://gitlab.freedesktop.org/drm/intel/issues/4387
[i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#4565]: https://gitlab.freedesktop.org/drm/intel/issues/4565
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767
[i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4818]: https://gitlab.freedesktop.org/drm/intel/issues/4818
[i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4853]: https://gitlab.freedesktop.org/drm/intel/issues/4853
[i915#4855]: https://gitlab.freedesktop.org/drm/intel/issues/4855
[i915#4859]: https://gitlab.freedesktop.org/drm/intel/issues/4859
[i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
[i915#4874]: https://gitlab.freedesktop.org/drm/intel/issues/4874
[i915#4879]: https://gitlab.freedesktop.org/drm/intel/issues/4879
[i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880
[i915#4881]: https://gitlab.freedesktop.org/drm/intel/issues/4881
[i915#4883]: https://gitlab.freedesktop.org/drm/intel/issues/4883
[i915#4884]: https://gitlab.freedesktop.org/drm/intel/issues/4884
[i915#4885]: https://gitlab.freedesktop.org/drm/intel/issues/4885
[i915#4893]: https://gitlab.freedesktop.org/drm/intel/issues/4893
[i915#4939]: https://gitlab.freedesktop.org/drm/intel/issues/4939
[i915#4941]: https://gitlab.freedesktop.org/drm/intel/issues/4941
[i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957
[i915#4958]: https://gitlab.freedesktop.org/drm/intel/issues/4958
[i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991
[i915#5122]: https://gitlab.freedesktop.org/drm/intel/issues/5122
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5287]: https://gitlab.freedesktop.org/drm/intel/issues/5287
[i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
[i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
[i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563
[i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
[i915#5723]: https://gitlab.freedesktop.org/drm/intel/issues/5723
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#5982]: https://gitlab.freedesktop.org/drm/intel/issues/5982
[i915#6011]: https://gitlab.freedesktop.org/drm/intel/issues/6011
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6245]: https://gitlab.freedesktop.org/drm/intel/issues/6245
[i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
[i915#6301]: https://gitlab.freedesktop.org/drm/intel/issues/6301
[i915#6331]: https://gitlab.freedesktop.org/drm/intel/issues/6331
[i915#6335]: https://gitlab.freedesktop.org/drm/intel/issues/6335
[i915#6412]: https://gitlab.freedesktop.org/drm/intel/issues/6412
[i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433
[i915#6458]: https://gitlab.freedesktop.org/drm/intel/issues/6458
[i915#6463]: https://gitlab.freedesktop.org/drm/intel/issues/6463
[i915#6493]: https://gitlab.freedesktop.org/drm/intel/issues/6493
[i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6590]: https://gitlab.freedesktop.org/drm/intel/issues/6590
[i915#6598]: https://gitlab.freedesktop.org/drm/intel/issues/6598
[i915#6599]: https://gitlab.freedesktop.org/drm/intel/issues/6599
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
Build changes
-------------
* Linux: CI_DRM_12003 -> Patchwork_107502v1
CI-20190529: 20190529
CI_DRM_12003: 5852b759ca0d67530d1dae6ab66c351e796fe39d @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6632: a0ac4d449e551fd5c78b56f85cd534330ea60507 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_107502v1: 5852b759ca0d67530d1dae6ab66c351e796fe39d @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107502v1/index.html
[-- Attachment #2: Type: text/html, Size: 29818 bytes --]
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [Intel-gfx] [PATCH] Revert "drm/i915/guc: Add delay to disable scheduling after pin count goes to zero"
2022-08-19 16:47 ` Teres Alexis, Alan Previn
@ 2022-09-01 15:49 ` Teres Alexis, Alan Previn
0 siblings, 0 replies; 7+ messages in thread
From: Teres Alexis, Alan Previn @ 2022-09-01 15:49 UTC (permalink / raw)
To: Harrison, John C
Cc: intel-gfx@lists.freedesktop.org, Auld, Matthew,
Teres Alexis, Alan Previn
I think i found the problem - will trybot next before reposting a new rev.
was a terribly careless typo when rebasing from internal for drmtip:
guc_context_sched_disable called do_sched_disable which was supposed to call __guc_context_sched_disable (if the context
was really meant to be finally disabled) but instead called guc_context_sched_disable (no underscore) causing an
infinite loop for mid-disabling.
...alan
On Fri, 2022-08-19 at 16:47 +0000, Teres Alexis, Alan Previn wrote:
> Will look into this - apologies for the trouble Matt.
> ...alan
>
> -----Original Message-----
> From: Harrison, John C <john.c.harrison@intel.com>
> Sent: Friday, August 19, 2022 8:46 AM
> To: Auld, Matthew <matthew.auld@intel.com>; intel-gfx@lists.freedesktop.org
> Cc: Brost, Matthew <matthew.brost@intel.com>; Teres Alexis, Alan Previn <alan.previn.teres.alexis@intel.com>
> Subject: Re: [PATCH] Revert "drm/i915/guc: Add delay to disable scheduling after pin count goes to zero"
>
> On 8/19/2022 05:39, Matthew Auld wrote:
> > This reverts commit 6a079903847cce1dd06345127d2a32f26d2cd9c6.
> >
> > Everything in CI using GuC is now timing out[1], and killing the
> > machine with this change (perhaps a deadlock?). CI was recently on
> > fire due to some changes coming in from -rc1, so likely the pre-merge
> > CI results for this series were invalid? For now just revert, unless
> > GuC experts already have a fix in mind.
> >
> > [1] https://intel-gfx-ci.01.org/tree/drm-tip/index.html?
> >
> > Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> > Cc: Matthew Brost <matthew.brost@intel.com>
> > Cc: Alan Previn <alan.previn.teres.alexis@intel.com>
> > Cc: John Harrison <John.C.Harrison@Intel.com>
> Reviewed-by: John Harrison <John.C.Harrison@Intel.com>
>
> Given that CI was claiming a pass for the original patch set, no we don't have a fix in mind. It is most frustrating when CI says all green if the entire universe is so broken that no tests were even running :(.
>
> John.
>
>
> > ---
> > drivers/gpu/drm/i915/gem/i915_gem_context.c | 2 +-
> > drivers/gpu/drm/i915/gt/intel_context.h | 8 -
> > drivers/gpu/drm/i915/gt/intel_context_types.h | 7 -
> > drivers/gpu/drm/i915/gt/uc/intel_guc.h | 17 +-
> > .../gpu/drm/i915/gt/uc/intel_guc_debugfs.c | 60 -------
> > .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 154 +++---------------
> > drivers/gpu/drm/i915/i915_selftest.h | 2 -
> > 7 files changed, 27 insertions(+), 223 deletions(-)
> >
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2022-09-01 15:50 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2022-08-19 12:39 [Intel-gfx] [PATCH] Revert "drm/i915/guc: Add delay to disable scheduling after pin count goes to zero" Matthew Auld
2022-08-19 13:25 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for " Patchwork
2022-08-19 13:48 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-08-19 15:46 ` [Intel-gfx] [PATCH] " John Harrison
2022-08-19 16:47 ` Teres Alexis, Alan Previn
2022-09-01 15:49 ` Teres Alexis, Alan Previn
2022-08-20 13:13 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for " Patchwork
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