From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 06/11] drm/i915/display: Consider fractional vdsc bpp while computing m_n values
Date: Mon, 28 Nov 2022 15:49:17 +0530 [thread overview]
Message-ID: <20221128101922.217217-7-ankit.k.nautiyal@intel.com> (raw)
In-Reply-To: <20221128101922.217217-1-ankit.k.nautiyal@intel.com>
MTL+ supports fractional compressed bits_per_pixel, with precision of
1/16. This compressed bpp is stored in U6.4 format.
Accommodate this precision while computing m_n values.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 6 +++++-
drivers/gpu/drm/i915/display/intel_display.h | 2 +-
drivers/gpu/drm/i915/display/intel_dp.c | 7 ++++---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 ++-
drivers/gpu/drm/i915/display/intel_fdi.c | 2 +-
5 files changed, 13 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index b3e23708d194..5a7703af166d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2753,10 +2753,14 @@ void
intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,
int pixel_clock, int link_clock,
struct intel_link_m_n *m_n,
- bool fec_enable)
+ bool fec_enable,
+ bool is_dsc_fractional_bpp)
{
u32 data_clock = bits_per_pixel * pixel_clock;
+ if (is_dsc_fractional_bpp)
+ data_clock = DIV_ROUND_UP(bits_per_pixel * pixel_clock, 16);
+
if (fec_enable)
data_clock = intel_dp_mode_to_fec_clock(data_clock);
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 714030136b7f..f3d32de9fa2c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -506,7 +506,7 @@ u8 intel_calc_active_pipes(struct intel_atomic_state *state,
void intel_link_compute_m_n(u16 bpp, int nlanes,
int pixel_clock, int link_clock,
struct intel_link_m_n *m_n,
- bool fec_enable);
+ bool fec_enable, bool is_dsc_fractional_bpp);
u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
u32 pixel_format, u64 modifier);
enum drm_mode_status
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 5f61abb8a0e2..7ad39ddadae6 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2132,7 +2132,7 @@ intel_dp_drrs_compute_config(struct intel_connector *connector,
intel_link_compute_m_n(output_bpp, pipe_config->lane_count, pixel_clock,
pipe_config->port_clock, &pipe_config->dp_m2_n2,
- pipe_config->fec_enable);
+ pipe_config->fec_enable, false);
/* FIXME: abstract this better */
if (pipe_config->splitter.enable)
@@ -2255,7 +2255,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
intel_dp_limited_color_range(pipe_config, conn_state);
if (pipe_config->dsc.compression_enable)
- output_bpp = dsc_integral_compressed_bpp(pipe_config->dsc.compressed_bpp);
+ output_bpp = pipe_config->dsc.compressed_bpp;
else
output_bpp = intel_dp_output_bpp(pipe_config->output_format,
pipe_config->pipe_bpp);
@@ -2285,7 +2285,8 @@ intel_dp_compute_config(struct intel_encoder *encoder,
adjusted_mode->crtc_clock,
pipe_config->port_clock,
&pipe_config->dp_m_n,
- pipe_config->fec_enable);
+ pipe_config->fec_enable,
+ pipe_config->dsc.compression_enable);
/* FIXME: abstract this better */
if (pipe_config->splitter.enable)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 4077a979a924..4f8010285ebf 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -100,7 +100,8 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
adjusted_mode->crtc_clock,
crtc_state->port_clock,
&crtc_state->dp_m_n,
- crtc_state->fec_enable);
+ crtc_state->fec_enable,
+ false);
crtc_state->dp_m_n.tu = slots;
return 0;
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
index 063f1da4f229..5ab6c2e983d5 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.c
+++ b/drivers/gpu/drm/i915/display/intel_fdi.c
@@ -257,7 +257,7 @@ int ilk_fdi_compute_config(struct intel_crtc *crtc,
pipe_config->fdi_lanes = lane;
intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
- link_bw, &pipe_config->fdi_m_n, false);
+ link_bw, &pipe_config->fdi_m_n, false, false);
ret = ilk_check_fdi_lanes(dev, crtc->pipe, pipe_config);
if (ret == -EDEADLK)
--
2.25.1
next prev parent reply other threads:[~2022-11-28 10:19 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-28 10:19 [Intel-gfx] [PATCH 00/11] Add DSC fractional bpp support Ankit Nautiyal
2022-11-28 10:19 ` [Intel-gfx] [PATCH 01/11] drm/i915/dp: Check if force dsc bpc <= max requested bpc Ankit Nautiyal
2022-11-28 10:19 ` [Intel-gfx] [PATCH 02/11] drm/display/dp: Add helper function to get DSC bpp prescision Ankit Nautiyal
2022-11-28 15:27 ` kernel test robot
2022-11-28 10:19 ` [Intel-gfx] [PATCH 03/11] drm/i915/dp: Rename helpers to get DSC max pipe bpp and max output bpp Ankit Nautiyal
2022-11-28 10:19 ` [Intel-gfx] [PATCH 04/11] drm/i915/dp: Get optimal link config to have best compressed bpp Ankit Nautiyal
2022-12-05 7:28 ` Lisovskiy, Stanislav
2022-12-06 10:15 ` Nautiyal, Ankit K
2022-11-28 10:19 ` [Intel-gfx] [PATCH 05/11] drm/i915/display: Store compressed bpp in U6.4 format Ankit Nautiyal
2022-11-28 10:19 ` Ankit Nautiyal [this message]
2022-11-28 10:19 ` [Intel-gfx] [PATCH 07/11] drm/i915/audio : Consider fractional vdsc bpp while computing tu_data Ankit Nautiyal
2022-12-05 7:35 ` Lisovskiy, Stanislav
2022-12-06 10:19 ` Nautiyal, Ankit K
2022-11-28 10:19 ` [Intel-gfx] [PATCH 08/11] drm/i915/dsc/mtl: Add support for fractional bpp Ankit Nautiyal
2022-11-28 10:19 ` [Intel-gfx] [PATCH 09/11] drm/i915/dp: Iterate over output bpp with fractional step size Ankit Nautiyal
2022-11-28 10:19 ` [Intel-gfx] [PATCH 10/11] drm/i915/dsc: Add debugfs entry to validate DSC fractional bpp Ankit Nautiyal
2022-11-28 10:19 ` [Intel-gfx] [PATCH 11/11] drm/i915/dsc: Allow DSC only with fractional bpp when forced from debugfs Ankit Nautiyal
2022-11-28 12:45 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add DSC fractional bpp support Patchwork
2022-11-28 12:45 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
2022-11-28 13:04 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-11-28 16:57 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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