From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 12/13] drm/i915/dsb: Define more DSB registers
Date: Fri, 16 Dec 2022 02:38:09 +0200 [thread overview]
Message-ID: <20221216003810.13338-13-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20221216003810.13338-1-ville.syrjala@linux.intel.com>
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Add definitions for more DSB registers. Less annoying spec
trawling when working on the DSB code.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 50 +++++++++++++++++++++++++++++++--
1 file changed, 48 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ed989e749635..3b0d07880c30 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8103,8 +8103,54 @@ enum skl_power_gate {
#define DSB_HEAD(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x0)
#define DSB_TAIL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x4)
#define DSB_CTRL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x8)
-#define DSB_ENABLE (1 << 31)
-#define DSB_STATUS_BUSY (1 << 0)
+#define DSB_ENABLE REG_BIT(31)
+#define DSB_BUF_REITERATE REG_BIT(29)
+#define DSB_WAIT_FOR_VBLANK REG_BIT(28)
+#define DSB_WAIT_FOR_LINE_IN REG_BIT(27)
+#define DSB_HALT REG_BIT(16)
+#define DSB_NON_POSTED REG_BIT(8)
+#define DSB_STATUS_BUSY REG_BIT(0)
+#define DSB_MMIOCTRL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0xc)
+#define DSB_MMIO_DEAD_CLOCKS_ENABLE REG_BIT(31)
+#define DSB_MMIO_DEAD_CLOCKS_COUNT_MASK REG_GENMASK(15, 8)
+#define DSB_MMIO_DEAD_CLOCKS_COUNT(x) REG_FIELD_PREP(DSB_MMIO_DEAD_CLOCK_COUNT_MASK, (x))
+#define DSB_MMIO_CYCLES_MASK REG_GENMASK(7, 0)
+#define DSB_MMIO_CYCLES(x) REG_FIELD_PREP(DSB_MMIO_CYCLES_MASK, (x))
+#define DSB_POLLFUNC(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x10)
+#define DSB_POLL_ENABLE REG_BIT(31)
+#define DSB_POLL_WAIT_MASK REG_GENMASK(30, 23)
+#define DSB_POLL_WAIT(x) REG_FIELD_PREP(DSB_POLL_WAIT_MASK, (x)) /* usec */
+#define DSB_POLL_COUNT_MASK REG_GENMASK(22, 15)
+#define DSB_POLL_COUNT(x) REG_FIELD_PREP(DSB_POLL_COUNT_MASK, (x))
+#define DSB_DEBUG(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x14)
+#define DSB_POLLMASK(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x1c)
+#define DSB_STATUS(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x24)
+#define DSB_INTERRUPT(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x28)
+#define DSB_ATS_FAULT_INT_EN REG_BIT(20)
+#define DSB_GTT_FAULT_INT_EN REG_BIT(19)
+#define DSB_RSPTIMEOUT_INT_EN REG_BIT(18)
+#define DSB_POLL_ERR_INT_EN REG_BIT(17)
+#define DSB_PROG_INT_EN REG_BIT(16)
+#define DSB_ATS_FAULT_INT_STATUS REG_BIT(4)
+#define DSB_GTT_FAULT_INT_STATUS REG_BIT(3)
+#define DSB_RSPTIMEOUT_INT_STATUS REG_BIT(2)
+#define DSB_POLL_ERR_INT_STATUS REG_BIT(1)
+#define DSB_PROG_INT_STATUS REG_BIT(0)
+#define DSB_CURRENT_HEAD(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x2c)
+#define DSB_RM_TIMEOUT(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x30)
+#define DSB_RM_CLAIM_TIMEOUT REG_BIT(31)
+#define DSB_RM_READY_TIMEOUT REG_BIT(30)
+#define DSB_RM_CLAIM_TIMEOUT_COUNT_MASK REG_GENMASK(23, 16)
+#define DSB_RM_CLAIM_TIMEOUT_COUNT(x) REG_FIELD_PREP(DSB_RM_CLAIM_TIMEOUT_COUNT_MASK, (x)) /* clocks */
+#define DSB_RM_READY_TIMEOUT_VALUE_MASK REG_GENMASK(15, 0)
+#define DSB_RM_READY_TIMEOUT_VALUE(x) REG_FIELD_PREP(DSB_RM_READY_TIMEOUT_VALUE, (x)) /* usec */
+#define DSB_RMTIMEOUTREG_CAPTURE(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x34)
+#define DSB_PMCTRL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x38)
+#define DSB_PMCTRL_2(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x3c)
+#define DSB_PF_LN_LOWER(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x40)
+#define DSB_PF_LN_UPPER(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x44)
+#define DSB_BUFRPT_CNT(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x48)
+#define DSB_CHICKEN(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0xf0)
#define CLKREQ_POLICY _MMIO(0x101038)
#define CLKREQ_POLICY_MEM_UP_OVRD REG_BIT(1)
--
2.37.4
next prev parent reply other threads:[~2022-12-16 0:39 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-16 0:37 [Intel-gfx] [PATCH 00/13] drm/i915/dsb: DSB fixes/cleanups Ville Syrjala
2022-12-16 0:37 ` [Intel-gfx] [PATCH 01/13] drm/i915/dsb: Stop with the RMW Ville Syrjala
2023-01-04 7:59 ` Manna, Animesh
2022-12-16 0:37 ` [Intel-gfx] [PATCH 02/13] drm/i915/dsb: Inline DSB_CTRL writes into intel_dsb_commit() Ville Syrjala
2023-01-04 8:40 ` Manna, Animesh
2022-12-16 0:38 ` [Intel-gfx] [PATCH 03/13] drm/i915/dsb: Align DSB register writes to 8 bytes Ville Syrjala
2023-01-04 9:08 ` Manna, Animesh
2022-12-16 0:38 ` [Intel-gfx] [PATCH 04/13] drm/i915/dsb: Fix DSB command buffer size checks Ville Syrjala
2023-01-04 6:57 ` Manna, Animesh
2023-01-04 7:11 ` Manna, Animesh
2023-01-04 10:52 ` Manna, Animesh
2022-12-16 0:38 ` [Intel-gfx] [PATCH 05/13] drm/i915/dsb: Extract assert_dsb_has_room() Ville Syrjala
2023-01-04 11:36 ` Manna, Animesh
2022-12-16 0:38 ` [Intel-gfx] [PATCH 06/13] drm/i915/dsb: Extract intel_dsb_emit() Ville Syrjala
2023-01-04 11:41 ` Manna, Animesh
2022-12-16 0:38 ` [Intel-gfx] [PATCH 07/13] drm/i915/dsb: Improve the indexed reg write checks Ville Syrjala
2023-01-04 12:13 ` Manna, Animesh
2022-12-16 0:38 ` [Intel-gfx] [PATCH 08/13] drm/i915/dsb: Handle the indexed vs. not inside the DSB code Ville Syrjala
2023-01-05 14:43 ` Manna, Animesh
2022-12-16 0:38 ` [Intel-gfx] [PATCH 09/13] drm/i915/dsb: Introduce intel_dsb_align_tail() Ville Syrjala
2023-01-05 14:46 ` Manna, Animesh
2022-12-16 0:38 ` [Intel-gfx] [PATCH 10/13] drm/i915/dsb: Allow the caller to pass in the DSB buffer size Ville Syrjala
2023-01-05 15:19 ` Manna, Animesh
2022-12-16 0:38 ` [Intel-gfx] [PATCH 11/13] drm/i915/dsb: Add mode DSB opcodes Ville Syrjala
2023-01-05 15:22 ` Manna, Animesh
2023-01-09 9:47 ` Jani Nikula
2023-01-11 12:43 ` Manna, Animesh
2022-12-16 0:38 ` Ville Syrjala [this message]
2023-01-11 15:59 ` [Intel-gfx] [PATCH 12/13] drm/i915/dsb: Define more DSB registers Manna, Animesh
2023-01-13 14:37 ` Ville Syrjälä
2022-12-16 0:38 ` [Intel-gfx] [PATCH 13/13] drm/i915/dsb: Pimp debug/error prints Ville Syrjala
2022-12-16 0:57 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dsb: DSB fixes/cleanups Patchwork
2022-12-16 0:57 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-12-16 1:31 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-12-16 15:54 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20221216003810.13338-13-ville.syrjala@linux.intel.com \
--to=ville.syrjala@linux.intel.com \
--cc=intel-gfx@lists.freedesktop.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox