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From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 01/13] drm/i915/dsb: Stop with the RMW
Date: Fri, 16 Dec 2022 02:37:58 +0200	[thread overview]
Message-ID: <20221216003810.13338-2-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20221216003810.13338-1-ville.syrjala@linux.intel.com>

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We don't want to keep random bits set in DSB_CTRL. Stop the
harmful RMW.

Also flip the reverse & around to appease my ocd.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dsb.c | 22 +++++++---------------
 drivers/gpu/drm/i915/i915_reg.h          |  2 +-
 2 files changed, 8 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
index 3d63c1bf1e4f..ebebaf802dee 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -73,42 +73,34 @@ struct intel_dsb {
 static bool is_dsb_busy(struct drm_i915_private *i915, enum pipe pipe,
 			enum dsb_id id)
 {
-	return DSB_STATUS & intel_de_read(i915, DSB_CTRL(pipe, id));
+	return intel_de_read(i915, DSB_CTRL(pipe, id)) & DSB_STATUS_BUSY;
 }
 
 static bool intel_dsb_enable_engine(struct drm_i915_private *i915,
 				    enum pipe pipe, enum dsb_id id)
 {
-	u32 dsb_ctrl;
-
-	dsb_ctrl = intel_de_read(i915, DSB_CTRL(pipe, id));
-	if (DSB_STATUS & dsb_ctrl) {
+	if (is_dsb_busy(i915, pipe, id)) {
 		drm_dbg_kms(&i915->drm, "DSB engine is busy.\n");
 		return false;
 	}
 
-	dsb_ctrl |= DSB_ENABLE;
-	intel_de_write(i915, DSB_CTRL(pipe, id), dsb_ctrl);
-
+	intel_de_write(i915, DSB_CTRL(pipe, id), DSB_ENABLE);
 	intel_de_posting_read(i915, DSB_CTRL(pipe, id));
+
 	return true;
 }
 
 static bool intel_dsb_disable_engine(struct drm_i915_private *i915,
 				     enum pipe pipe, enum dsb_id id)
 {
-	u32 dsb_ctrl;
-
-	dsb_ctrl = intel_de_read(i915, DSB_CTRL(pipe, id));
-	if (DSB_STATUS & dsb_ctrl) {
+	if (is_dsb_busy(i915, pipe, id)) {
 		drm_dbg_kms(&i915->drm, "DSB engine is busy.\n");
 		return false;
 	}
 
-	dsb_ctrl &= ~DSB_ENABLE;
-	intel_de_write(i915, DSB_CTRL(pipe, id), dsb_ctrl);
-
+	intel_de_write(i915, DSB_CTRL(pipe, id), 0);
 	intel_de_posting_read(i915, DSB_CTRL(pipe, id));
+
 	return true;
 }
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index cef9418beec0..ed989e749635 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8104,7 +8104,7 @@ enum skl_power_gate {
 #define DSB_TAIL(pipe, id)		_MMIO(DSBSL_INSTANCE(pipe, id) + 0x4)
 #define DSB_CTRL(pipe, id)		_MMIO(DSBSL_INSTANCE(pipe, id) + 0x8)
 #define   DSB_ENABLE			(1 << 31)
-#define   DSB_STATUS			(1 << 0)
+#define   DSB_STATUS_BUSY		(1 << 0)
 
 #define CLKREQ_POLICY			_MMIO(0x101038)
 #define  CLKREQ_POLICY_MEM_UP_OVRD	REG_BIT(1)
-- 
2.37.4


  reply	other threads:[~2022-12-16  0:38 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-12-16  0:37 [Intel-gfx] [PATCH 00/13] drm/i915/dsb: DSB fixes/cleanups Ville Syrjala
2022-12-16  0:37 ` Ville Syrjala [this message]
2023-01-04  7:59   ` [Intel-gfx] [PATCH 01/13] drm/i915/dsb: Stop with the RMW Manna, Animesh
2022-12-16  0:37 ` [Intel-gfx] [PATCH 02/13] drm/i915/dsb: Inline DSB_CTRL writes into intel_dsb_commit() Ville Syrjala
2023-01-04  8:40   ` Manna, Animesh
2022-12-16  0:38 ` [Intel-gfx] [PATCH 03/13] drm/i915/dsb: Align DSB register writes to 8 bytes Ville Syrjala
2023-01-04  9:08   ` Manna, Animesh
2022-12-16  0:38 ` [Intel-gfx] [PATCH 04/13] drm/i915/dsb: Fix DSB command buffer size checks Ville Syrjala
2023-01-04  6:57   ` Manna, Animesh
2023-01-04  7:11     ` Manna, Animesh
2023-01-04 10:52   ` Manna, Animesh
2022-12-16  0:38 ` [Intel-gfx] [PATCH 05/13] drm/i915/dsb: Extract assert_dsb_has_room() Ville Syrjala
2023-01-04 11:36   ` Manna, Animesh
2022-12-16  0:38 ` [Intel-gfx] [PATCH 06/13] drm/i915/dsb: Extract intel_dsb_emit() Ville Syrjala
2023-01-04 11:41   ` Manna, Animesh
2022-12-16  0:38 ` [Intel-gfx] [PATCH 07/13] drm/i915/dsb: Improve the indexed reg write checks Ville Syrjala
2023-01-04 12:13   ` Manna, Animesh
2022-12-16  0:38 ` [Intel-gfx] [PATCH 08/13] drm/i915/dsb: Handle the indexed vs. not inside the DSB code Ville Syrjala
2023-01-05 14:43   ` Manna, Animesh
2022-12-16  0:38 ` [Intel-gfx] [PATCH 09/13] drm/i915/dsb: Introduce intel_dsb_align_tail() Ville Syrjala
2023-01-05 14:46   ` Manna, Animesh
2022-12-16  0:38 ` [Intel-gfx] [PATCH 10/13] drm/i915/dsb: Allow the caller to pass in the DSB buffer size Ville Syrjala
2023-01-05 15:19   ` Manna, Animesh
2022-12-16  0:38 ` [Intel-gfx] [PATCH 11/13] drm/i915/dsb: Add mode DSB opcodes Ville Syrjala
2023-01-05 15:22   ` Manna, Animesh
2023-01-09  9:47     ` Jani Nikula
2023-01-11 12:43       ` Manna, Animesh
2022-12-16  0:38 ` [Intel-gfx] [PATCH 12/13] drm/i915/dsb: Define more DSB registers Ville Syrjala
2023-01-11 15:59   ` Manna, Animesh
2023-01-13 14:37     ` Ville Syrjälä
2022-12-16  0:38 ` [Intel-gfx] [PATCH 13/13] drm/i915/dsb: Pimp debug/error prints Ville Syrjala
2022-12-16  0:57 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dsb: DSB fixes/cleanups Patchwork
2022-12-16  0:57 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-12-16  1:31 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-12-16 15:54 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

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