From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 05/13] drm/i915/dsb: Extract assert_dsb_has_room()
Date: Fri, 16 Dec 2022 02:38:02 +0200 [thread overview]
Message-ID: <20221216003810.13338-6-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20221216003810.13338-1-ville.syrjala@linux.intel.com>
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Pull the DSB command buffer size checks into a small helper so
we don't have repeat the same thing multiple times.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_dsb.c | 22 ++++++++++++----------
1 file changed, 12 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
index fbcbf9efd039..6fc7d087a7ca 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -70,6 +70,16 @@ struct intel_dsb {
#define DSB_BYTE_EN_SHIFT 20
#define DSB_REG_VALUE_MASK 0xfffff
+static bool assert_dsb_has_room(struct intel_dsb *dsb)
+{
+ struct intel_crtc *crtc = dsb->crtc;
+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+
+ /* each instruction is 2 dwords */
+ return !drm_WARN(&i915->drm, ALIGN(dsb->free_pos, 2) > DSB_BUF_SIZE / 4 - 2,
+ "DSB buffer overflow\n");
+}
+
static bool is_dsb_busy(struct drm_i915_private *i915, enum pipe pipe,
enum dsb_id id)
{
@@ -92,15 +102,11 @@ static bool is_dsb_busy(struct drm_i915_private *i915, enum pipe pipe,
void intel_dsb_indexed_reg_write(struct intel_dsb *dsb,
i915_reg_t reg, u32 val)
{
- struct intel_crtc *crtc = dsb->crtc;
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
u32 *buf = dsb->cmd_buf;
u32 reg_val;
- if (drm_WARN_ON(&dev_priv->drm, ALIGN(dsb->free_pos, 2) > DSB_BUF_SIZE / 4 - 2)) {
- drm_dbg_kms(&dev_priv->drm, "DSB buffer overflow\n");
+ if (!assert_dsb_has_room(dsb))
return;
- }
/*
* For example the buffer will look like below for 3 dwords for auto
@@ -163,14 +169,10 @@ void intel_dsb_indexed_reg_write(struct intel_dsb *dsb,
void intel_dsb_reg_write(struct intel_dsb *dsb,
i915_reg_t reg, u32 val)
{
- struct intel_crtc *crtc = dsb->crtc;
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
u32 *buf = dsb->cmd_buf;
- if (drm_WARN_ON(&dev_priv->drm, ALIGN(dsb->free_pos, 2) > DSB_BUF_SIZE / 4 - 2)) {
- drm_dbg_kms(&dev_priv->drm, "DSB buffer overflow\n");
+ if (!assert_dsb_has_room(dsb))
return;
- }
/* Every instruction should be 8 byte aligned. */
dsb->free_pos = ALIGN(dsb->free_pos, 2);
--
2.37.4
next prev parent reply other threads:[~2022-12-16 0:39 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-16 0:37 [Intel-gfx] [PATCH 00/13] drm/i915/dsb: DSB fixes/cleanups Ville Syrjala
2022-12-16 0:37 ` [Intel-gfx] [PATCH 01/13] drm/i915/dsb: Stop with the RMW Ville Syrjala
2023-01-04 7:59 ` Manna, Animesh
2022-12-16 0:37 ` [Intel-gfx] [PATCH 02/13] drm/i915/dsb: Inline DSB_CTRL writes into intel_dsb_commit() Ville Syrjala
2023-01-04 8:40 ` Manna, Animesh
2022-12-16 0:38 ` [Intel-gfx] [PATCH 03/13] drm/i915/dsb: Align DSB register writes to 8 bytes Ville Syrjala
2023-01-04 9:08 ` Manna, Animesh
2022-12-16 0:38 ` [Intel-gfx] [PATCH 04/13] drm/i915/dsb: Fix DSB command buffer size checks Ville Syrjala
2023-01-04 6:57 ` Manna, Animesh
2023-01-04 7:11 ` Manna, Animesh
2023-01-04 10:52 ` Manna, Animesh
2022-12-16 0:38 ` Ville Syrjala [this message]
2023-01-04 11:36 ` [Intel-gfx] [PATCH 05/13] drm/i915/dsb: Extract assert_dsb_has_room() Manna, Animesh
2022-12-16 0:38 ` [Intel-gfx] [PATCH 06/13] drm/i915/dsb: Extract intel_dsb_emit() Ville Syrjala
2023-01-04 11:41 ` Manna, Animesh
2022-12-16 0:38 ` [Intel-gfx] [PATCH 07/13] drm/i915/dsb: Improve the indexed reg write checks Ville Syrjala
2023-01-04 12:13 ` Manna, Animesh
2022-12-16 0:38 ` [Intel-gfx] [PATCH 08/13] drm/i915/dsb: Handle the indexed vs. not inside the DSB code Ville Syrjala
2023-01-05 14:43 ` Manna, Animesh
2022-12-16 0:38 ` [Intel-gfx] [PATCH 09/13] drm/i915/dsb: Introduce intel_dsb_align_tail() Ville Syrjala
2023-01-05 14:46 ` Manna, Animesh
2022-12-16 0:38 ` [Intel-gfx] [PATCH 10/13] drm/i915/dsb: Allow the caller to pass in the DSB buffer size Ville Syrjala
2023-01-05 15:19 ` Manna, Animesh
2022-12-16 0:38 ` [Intel-gfx] [PATCH 11/13] drm/i915/dsb: Add mode DSB opcodes Ville Syrjala
2023-01-05 15:22 ` Manna, Animesh
2023-01-09 9:47 ` Jani Nikula
2023-01-11 12:43 ` Manna, Animesh
2022-12-16 0:38 ` [Intel-gfx] [PATCH 12/13] drm/i915/dsb: Define more DSB registers Ville Syrjala
2023-01-11 15:59 ` Manna, Animesh
2023-01-13 14:37 ` Ville Syrjälä
2022-12-16 0:38 ` [Intel-gfx] [PATCH 13/13] drm/i915/dsb: Pimp debug/error prints Ville Syrjala
2022-12-16 0:57 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dsb: DSB fixes/cleanups Patchwork
2022-12-16 0:57 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-12-16 1:31 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-12-16 15:54 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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