* [Intel-gfx] [PATCH 0/3] Fixes for various UC related issues
@ 2022-12-20 2:41 John.C.Harrison
2022-12-20 2:41 ` [Intel-gfx] [PATCH 1/3] drm/i915/guc: Fix missing return code checks in submission init John.C.Harrison
` (3 more replies)
0 siblings, 4 replies; 8+ messages in thread
From: John.C.Harrison @ 2022-12-20 2:41 UTC (permalink / raw)
To: Intel-GFX; +Cc: DRI-Devel
From: John Harrison <John.C.Harrison@Intel.com>
Fix a bunch of assorted issues with firmware loading and GuC
intialisation.
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
John Harrison (3):
drm/i915/guc: Fix missing return code checks in submission init
drm/i915/guc: Fix a static analysis warning
drm/i915/uc: Fix two issues with over-size firmware files
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 75 ++++++++++++++-----
.../gpu/drm/i915/gt/uc/intel_guc_submission.h | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 7 +-
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 42 +++++++----
4 files changed, 91 insertions(+), 35 deletions(-)
--
2.39.0
^ permalink raw reply [flat|nested] 8+ messages in thread
* [Intel-gfx] [PATCH 1/3] drm/i915/guc: Fix missing return code checks in submission init
2022-12-20 2:41 [Intel-gfx] [PATCH 0/3] Fixes for various UC related issues John.C.Harrison
@ 2022-12-20 2:41 ` John.C.Harrison
2022-12-20 2:41 ` [Intel-gfx] [PATCH 2/3] drm/i915/guc: Fix a static analysis warning John.C.Harrison
` (2 subsequent siblings)
3 siblings, 0 replies; 8+ messages in thread
From: John.C.Harrison @ 2022-12-20 2:41 UTC (permalink / raw)
To: Intel-GFX; +Cc: DRI-Devel
From: John Harrison <John.C.Harrison@Intel.com>
The CI results for the 'fast request' patch set (enables error return
codes for fire-and-forget H2G messages) hit an issue with the KMD
sending context submission requests on an invalid context. That was
caused by a fault injection probe failing the context creation of a
kernel context. However, there was no return code checking on any of
the kernel context registration paths. So the driver kept going and
tried to use the kernel context for the record defaults process.
Fix that by checking for errors and aborting as appropriate when
creating kernel contexts. While at it, clean up some other submission
init related failure cleanup paths. Also, rename guc_init_lrc_mapping
to guc_init_submission as the former name hasn't been valid in a long
time.
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 74 ++++++++++++++-----
.../gpu/drm/i915/gt/uc/intel_guc_submission.h | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 7 +-
3 files changed, 62 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 53f7f599cde3a..4682ec1dbd9c0 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1431,21 +1431,25 @@ static int guc_action_enable_usage_stats(struct intel_guc *guc)
return intel_guc_send(guc, action, ARRAY_SIZE(action));
}
-static void guc_init_engine_stats(struct intel_guc *guc)
+static int guc_init_engine_stats(struct intel_guc *guc)
{
struct intel_gt *gt = guc_to_gt(guc);
intel_wakeref_t wakeref;
+ int ret;
mod_delayed_work(system_highpri_wq, &guc->timestamp.work,
guc->timestamp.ping_delay);
with_intel_runtime_pm(>->i915->runtime_pm, wakeref) {
- int ret = guc_action_enable_usage_stats(guc);
+ ret = guc_action_enable_usage_stats(guc);
- if (ret)
- drm_err(>->i915->drm,
- "Failed to enable usage stats: %d!\n", ret);
+ if (ret) {
+ cancel_delayed_work_sync(&guc->timestamp.work);
+ drm_err(>->i915->drm, "Failed to enable usage stats: %d!\n", ret);
+ }
}
+
+ return ret;
}
void intel_guc_busyness_park(struct intel_gt *gt)
@@ -4101,9 +4105,11 @@ static void guc_set_default_submission(struct intel_engine_cs *engine)
engine->submit_request = guc_submit_request;
}
-static inline void guc_kernel_context_pin(struct intel_guc *guc,
- struct intel_context *ce)
+static inline int guc_kernel_context_pin(struct intel_guc *guc,
+ struct intel_context *ce)
{
+ int ret;
+
/*
* Note: we purposefully do not check the returns below because
* the registration can only fail if a reset is just starting.
@@ -4111,16 +4117,24 @@ static inline void guc_kernel_context_pin(struct intel_guc *guc,
* isn't happening and even it did this code would be run again.
*/
- if (context_guc_id_invalid(ce))
- pin_guc_id(guc, ce);
+ if (context_guc_id_invalid(ce)) {
+ int ret = pin_guc_id(guc, ce);
+
+ if (ret < 0)
+ return ret;
+ }
if (!test_bit(CONTEXT_GUC_INIT, &ce->flags))
guc_context_init(ce);
- try_context_registration(ce, true);
+ ret = try_context_registration(ce, true);
+ if (ret)
+ unpin_guc_id(guc, ce);
+
+ return ret;
}
-static inline void guc_init_lrc_mapping(struct intel_guc *guc)
+static inline int guc_init_submission(struct intel_guc *guc)
{
struct intel_gt *gt = guc_to_gt(guc);
struct intel_engine_cs *engine;
@@ -4147,9 +4161,17 @@ static inline void guc_init_lrc_mapping(struct intel_guc *guc)
struct intel_context *ce;
list_for_each_entry(ce, &engine->pinned_contexts_list,
- pinned_contexts_link)
- guc_kernel_context_pin(guc, ce);
+ pinned_contexts_link) {
+ int ret = guc_kernel_context_pin(guc, ce);
+
+ if (ret) {
+ /* No point in trying to clean up as i915 will wedge on failure */
+ return ret;
+ }
+ }
}
+
+ return 0;
}
static void guc_release(struct intel_engine_cs *engine)
@@ -4391,9 +4413,10 @@ static int guc_init_global_schedule_policy(struct intel_guc *guc)
return ret;
}
-void intel_guc_submission_enable(struct intel_guc *guc)
+int intel_guc_submission_enable(struct intel_guc *guc)
{
struct intel_gt *gt = guc_to_gt(guc);
+ int ret;
/* Enable and route to GuC */
if (GRAPHICS_VER(gt->i915) >= 12)
@@ -4401,16 +4424,31 @@ void intel_guc_submission_enable(struct intel_guc *guc)
GUC_SEM_INTR_ROUTE_TO_GUC |
GUC_SEM_INTR_ENABLE_ALL);
- guc_init_lrc_mapping(guc);
- guc_init_engine_stats(guc);
- guc_init_global_schedule_policy(guc);
+ ret = guc_init_submission(guc);
+ if (ret)
+ goto fail;
+
+ ret = guc_init_engine_stats(guc);
+ if (ret)
+ goto fail;
+
+ ret = guc_init_global_schedule_policy(guc);
+ if (ret)
+ goto fail;
+
+ return 0;
+
+fail:
+ intel_guc_submission_disable(guc);
+ return ret;
}
+/* Note: By the time we're here, GuC may have already been reset */
void intel_guc_submission_disable(struct intel_guc *guc)
{
struct intel_gt *gt = guc_to_gt(guc);
- /* Note: By the time we're here, GuC may have already been reset */
+ cancel_delayed_work_sync(&guc->timestamp.work);
/* Disable and route to host */
if (GRAPHICS_VER(gt->i915) >= 12)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.h
index 5a95a9f0a8e31..c57b29cdb1a64 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.h
@@ -15,7 +15,7 @@ struct intel_engine_cs;
void intel_guc_submission_init_early(struct intel_guc *guc);
int intel_guc_submission_init(struct intel_guc *guc);
-void intel_guc_submission_enable(struct intel_guc *guc);
+int intel_guc_submission_enable(struct intel_guc *guc);
void intel_guc_submission_disable(struct intel_guc *guc);
void intel_guc_submission_fini(struct intel_guc *guc);
int intel_guc_preempt_work_create(struct intel_guc *guc);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index 9a8a1abf71d7f..8e338b3321a93 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -537,8 +537,11 @@ static int __uc_init_hw(struct intel_uc *uc)
else
intel_huc_auth(huc);
- if (intel_uc_uses_guc_submission(uc))
- intel_guc_submission_enable(guc);
+ if (intel_uc_uses_guc_submission(uc)) {
+ ret = intel_guc_submission_enable(guc);
+ if (ret)
+ goto err_log_capture;
+ }
if (intel_uc_uses_guc_slpc(uc)) {
ret = intel_guc_slpc_enable(&guc->slpc);
--
2.39.0
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [Intel-gfx] [PATCH 2/3] drm/i915/guc: Fix a static analysis warning
2022-12-20 2:41 [Intel-gfx] [PATCH 0/3] Fixes for various UC related issues John.C.Harrison
2022-12-20 2:41 ` [Intel-gfx] [PATCH 1/3] drm/i915/guc: Fix missing return code checks in submission init John.C.Harrison
@ 2022-12-20 2:41 ` John.C.Harrison
2022-12-20 2:41 ` [Intel-gfx] [PATCH 3/3] drm/i915/uc: Fix two issues with over-size firmware files John.C.Harrison
2022-12-21 17:35 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Fixes for various UC related issues Patchwork
3 siblings, 0 replies; 8+ messages in thread
From: John.C.Harrison @ 2022-12-20 2:41 UTC (permalink / raw)
To: Intel-GFX; +Cc: DRI-Devel
From: John Harrison <John.C.Harrison@Intel.com>
A static analyser was complaining about not checking for null
pointers. However, the location of the complaint can only be reached
in the first place if said pointer is non-null. Basically, if we are
using a v69 GuC then the descriptor pool is guaranteed to be alocated
at start of day or submission will be disabled with an ENOMEM error.
And if we are using a later GuC that does not use a descriptor pool
then the v69 submission function would not be called. So, not a
possible null at that point in the code.
Hence adding a GEM_BUG_ON(!ptr) to keep the tool happy.
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
---
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 4682ec1dbd9c0..c93d0594bfd5e 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -2538,6 +2538,7 @@ static void prepare_context_registration_info_v69(struct intel_context *ce)
i915_gem_object_is_lmem(ce->ring->vma->obj));
desc = __get_lrc_desc_v69(guc, ctx_id);
+ GEM_BUG_ON(!desc);
desc->engine_class = engine_class_to_guc_class(engine->class);
desc->engine_submit_mask = engine->logical_mask;
desc->hw_context_desc = ce->lrc.lrca;
--
2.39.0
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [Intel-gfx] [PATCH 3/3] drm/i915/uc: Fix two issues with over-size firmware files
2022-12-20 2:41 [Intel-gfx] [PATCH 0/3] Fixes for various UC related issues John.C.Harrison
2022-12-20 2:41 ` [Intel-gfx] [PATCH 1/3] drm/i915/guc: Fix missing return code checks in submission init John.C.Harrison
2022-12-20 2:41 ` [Intel-gfx] [PATCH 2/3] drm/i915/guc: Fix a static analysis warning John.C.Harrison
@ 2022-12-20 2:41 ` John.C.Harrison
2022-12-20 11:15 ` Ceraolo Spurio, Daniele
2022-12-21 17:35 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Fixes for various UC related issues Patchwork
3 siblings, 1 reply; 8+ messages in thread
From: John.C.Harrison @ 2022-12-20 2:41 UTC (permalink / raw)
To: Intel-GFX
Cc: Thomas Hellström, Alan Previn, Jani Nikula, DRI-Devel,
Matthew Auld, Rodrigo Vivi
From: John Harrison <John.C.Harrison@Intel.com>
In the case where a firmware file is too large (e.g. someone
downloaded a web page ASCII dump from github...), the firmware object
is released but the pointer is not zerod. If no other firmware file
was found then release would be called again leading to a double kfree.
Also, the size check was only being applied to the initial firmware
load not any of the subsequent attempts. So move the check into a
wrapper that is used for all loads.
Fixes: 016241168dc5 ("drm/i915/uc: use different ggtt pin offsets for uc loads")
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Alan Previn <alan.previn.teres.alexis@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Matthew Auld <matthew.auld@intel.com>
Cc: "Thomas Hellström" <thomas.hellstrom@linux.intel.com>
---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 42 ++++++++++++++++--------
1 file changed, 28 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index d6ff6c584c1e1..06b5f92ba3a55 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -675,6 +675,32 @@ static int check_fw_header(struct intel_gt *gt,
return 0;
}
+int try_firmware_load(struct intel_uc_fw *uc_fw, const struct firmware **fw)
+{
+ struct intel_gt *gt = __uc_fw_to_gt(uc_fw);
+ struct device *dev = gt->i915->drm.dev;
+ int err;
+
+ err = firmware_request_nowarn(fw, uc_fw->file_selected.path, dev);
+
+ if (err)
+ return err;
+
+ if ((*fw)->size > INTEL_UC_RSVD_GGTT_PER_FW) {
+ drm_err(>->i915->drm,
+ "%s firmware %s: size (%zuKB) exceeds max supported size (%uKB)\n",
+ intel_uc_fw_type_repr(uc_fw->type), uc_fw->file_selected.path,
+ (*fw)->size / SZ_1K, INTEL_UC_RSVD_GGTT_PER_FW / SZ_1K);
+
+ /* try to find another blob to load */
+ release_firmware(*fw);
+ *fw = NULL;
+ return -ENOENT;
+ }
+
+ return 0;
+}
+
/**
* intel_uc_fw_fetch - fetch uC firmware
* @uc_fw: uC firmware
@@ -688,7 +714,6 @@ int intel_uc_fw_fetch(struct intel_uc_fw *uc_fw)
struct intel_gt *gt = __uc_fw_to_gt(uc_fw);
struct drm_i915_private *i915 = gt->i915;
struct intel_uc_fw_file file_ideal;
- struct device *dev = i915->drm.dev;
struct drm_i915_gem_object *obj;
const struct firmware *fw = NULL;
bool old_ver = false;
@@ -704,20 +729,9 @@ int intel_uc_fw_fetch(struct intel_uc_fw *uc_fw)
__force_fw_fetch_failures(uc_fw, -EINVAL);
__force_fw_fetch_failures(uc_fw, -ESTALE);
- err = firmware_request_nowarn(&fw, uc_fw->file_selected.path, dev);
+ err = try_firmware_load(uc_fw, &fw);
memcpy(&file_ideal, &uc_fw->file_wanted, sizeof(file_ideal));
- if (!err && fw->size > INTEL_UC_RSVD_GGTT_PER_FW) {
- drm_err(&i915->drm,
- "%s firmware %s: size (%zuKB) exceeds max supported size (%uKB)\n",
- intel_uc_fw_type_repr(uc_fw->type), uc_fw->file_selected.path,
- fw->size / SZ_1K, INTEL_UC_RSVD_GGTT_PER_FW / SZ_1K);
-
- /* try to find another blob to load */
- release_firmware(fw);
- err = -ENOENT;
- }
-
/* Any error is terminal if overriding. Don't bother searching for older versions */
if (err && intel_uc_fw_is_overridden(uc_fw))
goto fail;
@@ -738,7 +752,7 @@ int intel_uc_fw_fetch(struct intel_uc_fw *uc_fw)
break;
}
- err = firmware_request_nowarn(&fw, uc_fw->file_selected.path, dev);
+ err = try_firmware_load(uc_fw, &fw);
}
if (err)
--
2.39.0
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [Intel-gfx] [PATCH 3/3] drm/i915/uc: Fix two issues with over-size firmware files
2022-12-20 2:41 ` [Intel-gfx] [PATCH 3/3] drm/i915/uc: Fix two issues with over-size firmware files John.C.Harrison
@ 2022-12-20 11:15 ` Ceraolo Spurio, Daniele
0 siblings, 0 replies; 8+ messages in thread
From: Ceraolo Spurio, Daniele @ 2022-12-20 11:15 UTC (permalink / raw)
To: John.C.Harrison, Intel-GFX
Cc: Thomas Hellström, Alan Previn, Jani Nikula, DRI-Devel,
Matthew Auld, Rodrigo Vivi
On 12/20/2022 3:41 AM, John.C.Harrison@Intel.com wrote:
> From: John Harrison <John.C.Harrison@Intel.com>
>
> In the case where a firmware file is too large (e.g. someone
> downloaded a web page ASCII dump from github...), the firmware object
> is released but the pointer is not zerod. If no other firmware file
> was found then release would be called again leading to a double kfree.
>
> Also, the size check was only being applied to the initial firmware
> load not any of the subsequent attempts. So move the check into a
> wrapper that is used for all loads.
>
> Fixes: 016241168dc5 ("drm/i915/uc: use different ggtt pin offsets for uc loads")
> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Alan Previn <alan.previn.teres.alexis@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Matthew Auld <matthew.auld@intel.com>
> Cc: "Thomas Hellström" <thomas.hellstrom@linux.intel.com>
There was another patch that was sent to fix the double free
(https://patchwork.freedesktop.org/series/111545/), but this one is
better because it also fixes the size check.
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Daniele
> ---
> drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 42 ++++++++++++++++--------
> 1 file changed, 28 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
> index d6ff6c584c1e1..06b5f92ba3a55 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
> @@ -675,6 +675,32 @@ static int check_fw_header(struct intel_gt *gt,
> return 0;
> }
>
> +int try_firmware_load(struct intel_uc_fw *uc_fw, const struct firmware **fw)
> +{
> + struct intel_gt *gt = __uc_fw_to_gt(uc_fw);
> + struct device *dev = gt->i915->drm.dev;
> + int err;
> +
> + err = firmware_request_nowarn(fw, uc_fw->file_selected.path, dev);
> +
> + if (err)
> + return err;
> +
> + if ((*fw)->size > INTEL_UC_RSVD_GGTT_PER_FW) {
> + drm_err(>->i915->drm,
> + "%s firmware %s: size (%zuKB) exceeds max supported size (%uKB)\n",
> + intel_uc_fw_type_repr(uc_fw->type), uc_fw->file_selected.path,
> + (*fw)->size / SZ_1K, INTEL_UC_RSVD_GGTT_PER_FW / SZ_1K);
> +
> + /* try to find another blob to load */
> + release_firmware(*fw);
> + *fw = NULL;
> + return -ENOENT;
> + }
> +
> + return 0;
> +}
> +
> /**
> * intel_uc_fw_fetch - fetch uC firmware
> * @uc_fw: uC firmware
> @@ -688,7 +714,6 @@ int intel_uc_fw_fetch(struct intel_uc_fw *uc_fw)
> struct intel_gt *gt = __uc_fw_to_gt(uc_fw);
> struct drm_i915_private *i915 = gt->i915;
> struct intel_uc_fw_file file_ideal;
> - struct device *dev = i915->drm.dev;
> struct drm_i915_gem_object *obj;
> const struct firmware *fw = NULL;
> bool old_ver = false;
> @@ -704,20 +729,9 @@ int intel_uc_fw_fetch(struct intel_uc_fw *uc_fw)
> __force_fw_fetch_failures(uc_fw, -EINVAL);
> __force_fw_fetch_failures(uc_fw, -ESTALE);
>
> - err = firmware_request_nowarn(&fw, uc_fw->file_selected.path, dev);
> + err = try_firmware_load(uc_fw, &fw);
> memcpy(&file_ideal, &uc_fw->file_wanted, sizeof(file_ideal));
>
> - if (!err && fw->size > INTEL_UC_RSVD_GGTT_PER_FW) {
> - drm_err(&i915->drm,
> - "%s firmware %s: size (%zuKB) exceeds max supported size (%uKB)\n",
> - intel_uc_fw_type_repr(uc_fw->type), uc_fw->file_selected.path,
> - fw->size / SZ_1K, INTEL_UC_RSVD_GGTT_PER_FW / SZ_1K);
> -
> - /* try to find another blob to load */
> - release_firmware(fw);
> - err = -ENOENT;
> - }
> -
> /* Any error is terminal if overriding. Don't bother searching for older versions */
> if (err && intel_uc_fw_is_overridden(uc_fw))
> goto fail;
> @@ -738,7 +752,7 @@ int intel_uc_fw_fetch(struct intel_uc_fw *uc_fw)
> break;
> }
>
> - err = firmware_request_nowarn(&fw, uc_fw->file_selected.path, dev);
> + err = try_firmware_load(uc_fw, &fw);
> }
>
> if (err)
^ permalink raw reply [flat|nested] 8+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BUILD: failure for Fixes for various UC related issues
2022-12-20 2:41 [Intel-gfx] [PATCH 0/3] Fixes for various UC related issues John.C.Harrison
` (2 preceding siblings ...)
2022-12-20 2:41 ` [Intel-gfx] [PATCH 3/3] drm/i915/uc: Fix two issues with over-size firmware files John.C.Harrison
@ 2022-12-21 17:35 ` Patchwork
3 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2022-12-21 17:35 UTC (permalink / raw)
To: john.c.harrison; +Cc: intel-gfx
== Series Details ==
Series: Fixes for various UC related issues
URL : https://patchwork.freedesktop.org/series/112080/
State : failure
== Summary ==
Error: make failed
CALL scripts/checksyscalls.sh
DESCEND objtool
CC [M] drivers/gpu/drm/i915/gt/uc/intel_uc_fw.o
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:678:5: error: no previous prototype for ‘try_firmware_load’ [-Werror=missing-prototypes]
678 | int try_firmware_load(struct intel_uc_fw *uc_fw, const struct firmware **fw)
| ^~~~~~~~~~~~~~~~~
cc1: all warnings being treated as errors
make[5]: *** [scripts/Makefile.build:250: drivers/gpu/drm/i915/gt/uc/intel_uc_fw.o] Error 1
make[4]: *** [scripts/Makefile.build:500: drivers/gpu/drm/i915] Error 2
make[3]: *** [scripts/Makefile.build:500: drivers/gpu/drm] Error 2
make[2]: *** [scripts/Makefile.build:500: drivers/gpu] Error 2
make[1]: *** [scripts/Makefile.build:500: drivers] Error 2
make: *** [Makefile:1992: .] Error 2
^ permalink raw reply [flat|nested] 8+ messages in thread
* [Intel-gfx] [PATCH 2/3] drm/i915/guc: Fix a static analysis warning
2022-12-21 19:30 [Intel-gfx] [PATCH 0/3] " John.C.Harrison
@ 2022-12-21 19:30 ` John.C.Harrison
2022-12-22 12:57 ` Ceraolo Spurio, Daniele
0 siblings, 1 reply; 8+ messages in thread
From: John.C.Harrison @ 2022-12-21 19:30 UTC (permalink / raw)
To: Intel-GFX; +Cc: DRI-Devel
From: John Harrison <John.C.Harrison@Intel.com>
A static analyser was complaining about not checking for null
pointers. However, the location of the complaint can only be reached
in the first place if said pointer is non-null. Basically, if we are
using a v69 GuC then the descriptor pool is guaranteed to be alocated
at start of day or submission will be disabled with an ENOMEM error.
And if we are using a later GuC that does not use a descriptor pool
then the v69 submission function would not be called. So, not a
possible null at that point in the code.
Hence adding a GEM_BUG_ON(!ptr) to keep the tool happy.
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
---
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 4682ec1dbd9c0..c93d0594bfd5e 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -2538,6 +2538,7 @@ static void prepare_context_registration_info_v69(struct intel_context *ce)
i915_gem_object_is_lmem(ce->ring->vma->obj));
desc = __get_lrc_desc_v69(guc, ctx_id);
+ GEM_BUG_ON(!desc);
desc->engine_class = engine_class_to_guc_class(engine->class);
desc->engine_submit_mask = engine->logical_mask;
desc->hw_context_desc = ce->lrc.lrca;
--
2.39.0
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [Intel-gfx] [PATCH 2/3] drm/i915/guc: Fix a static analysis warning
2022-12-21 19:30 ` [Intel-gfx] [PATCH 2/3] drm/i915/guc: Fix a static analysis warning John.C.Harrison
@ 2022-12-22 12:57 ` Ceraolo Spurio, Daniele
0 siblings, 0 replies; 8+ messages in thread
From: Ceraolo Spurio, Daniele @ 2022-12-22 12:57 UTC (permalink / raw)
To: John.C.Harrison, Intel-GFX; +Cc: DRI-Devel
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Daniele
On 12/21/2022 8:30 PM, John.C.Harrison@Intel.com wrote:
> From: John Harrison <John.C.Harrison@Intel.com>
>
> A static analyser was complaining about not checking for null
> pointers. However, the location of the complaint can only be reached
> in the first place if said pointer is non-null. Basically, if we are
> using a v69 GuC then the descriptor pool is guaranteed to be alocated
> at start of day or submission will be disabled with an ENOMEM error.
> And if we are using a later GuC that does not use a descriptor pool
> then the v69 submission function would not be called. So, not a
> possible null at that point in the code.
>
> Hence adding a GEM_BUG_ON(!ptr) to keep the tool happy.
>
> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
> ---
> drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> index 4682ec1dbd9c0..c93d0594bfd5e 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> @@ -2538,6 +2538,7 @@ static void prepare_context_registration_info_v69(struct intel_context *ce)
> i915_gem_object_is_lmem(ce->ring->vma->obj));
>
> desc = __get_lrc_desc_v69(guc, ctx_id);
> + GEM_BUG_ON(!desc);
> desc->engine_class = engine_class_to_guc_class(engine->class);
> desc->engine_submit_mask = engine->logical_mask;
> desc->hw_context_desc = ce->lrc.lrca;
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2022-12-22 12:57 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2022-12-20 2:41 [Intel-gfx] [PATCH 0/3] Fixes for various UC related issues John.C.Harrison
2022-12-20 2:41 ` [Intel-gfx] [PATCH 1/3] drm/i915/guc: Fix missing return code checks in submission init John.C.Harrison
2022-12-20 2:41 ` [Intel-gfx] [PATCH 2/3] drm/i915/guc: Fix a static analysis warning John.C.Harrison
2022-12-20 2:41 ` [Intel-gfx] [PATCH 3/3] drm/i915/uc: Fix two issues with over-size firmware files John.C.Harrison
2022-12-20 11:15 ` Ceraolo Spurio, Daniele
2022-12-21 17:35 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Fixes for various UC related issues Patchwork
-- strict thread matches above, loose matches on Subject: below --
2022-12-21 19:30 [Intel-gfx] [PATCH 0/3] " John.C.Harrison
2022-12-21 19:30 ` [Intel-gfx] [PATCH 2/3] drm/i915/guc: Fix a static analysis warning John.C.Harrison
2022-12-22 12:57 ` Ceraolo Spurio, Daniele
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox