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From: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: ville.syrjala@intel.com
Subject: [Intel-gfx] [RFC 0/4] Add new CDCLK step for RPL-U
Date: Mon,  2 Jan 2023 11:50:01 +0530	[thread overview]
Message-ID: <20230102062005.720964-1-chaitanya.kumar.borah@intel.com> (raw)

A new step of 480MHz has been added on SKUs that have a RPL-U
device id. This particular step is to support 120Hz panels
more efficiently.

This patchset adds a new table to include this new CDCLK
step. Details can be found in BSpec entry 55409.

RPL-U device ids are currently added within the RPL-P sub
platform. It seems to be an overkill to add a separate sub
platform just to support this change. Therefore, quirks
are a good way to achieve this.

In addition to identifying RPL-U device id, we need to make a
distinction between ES and QS parts as this change comes only to
QS parts. CPUID Brand string is the only way to make this distinction
currently. ES parts have "Genuine Intel" in their brand string
while QS parts have a more specific brand string, for ex.
"13th Gen Intel(R) Core(TM) i5-1345U". Therefore, 480Mhz step is only
supported in SKUs which does not contain the string "Genuine Intel" in
the Brand string.

The patch "drm/i915: Apply CDCLK quirk only on QS parts" adds this
change. We have separated this patch because we request feedback
from the community if this change needs to be upstreamed or not
as ES parts will be deprecated in future. Feedbacks are welcome.

Chaitanya Kumar Borah (4):
  drm/i915/quirks: Add quirk for 480MHz CDCLK step
  drm/i915/display: Add 480 MHz CDCLK steps for RPL-U
  drm/i915: Initialize intel quirks before CDCLK initialization
  drm/i915: Apply CDCLK quirk only on QS parts

 drivers/gpu/drm/i915/display/intel_cdclk.c   | 25 ++++++++++++
 drivers/gpu/drm/i915/display/intel_display.c |  2 -
 drivers/gpu/drm/i915/display/intel_quirks.c  | 40 ++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_quirks.h  |  1 +
 drivers/gpu/drm/i915/i915_driver.c           |  2 +
 5 files changed, 68 insertions(+), 2 deletions(-)

-- 
2.25.1


             reply	other threads:[~2023-01-02  6:20 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-01-02  6:20 Chaitanya Kumar Borah [this message]
2023-01-02  6:20 ` [Intel-gfx] [RFC 1/4] drm/i915/quirks: Add quirk for 480MHz CDCLK step Chaitanya Kumar Borah
2023-01-02 10:03   ` Jani Nikula
2023-01-02 10:39     ` Jani Nikula
2023-01-07  5:52     ` Borah, Chaitanya Kumar
2023-01-02  6:20 ` [Intel-gfx] [RFC 2/4] drm/i915/display: Add 480 MHz CDCLK steps for RPL-U Chaitanya Kumar Borah
2023-01-02 10:05   ` Jani Nikula
2023-01-02  6:20 ` [Intel-gfx] [RFC 3/4] drm/i915: Initialize intel quirks before CDCLK initialization Chaitanya Kumar Borah
2023-01-02 10:07   ` Jani Nikula
2023-01-02  6:20 ` [Intel-gfx] [RFC 4/4] drm/i915: Apply CDCLK quirk only on QS parts Chaitanya Kumar Borah
2023-01-02 10:03 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for Add new CDCLK step for RPL-U (rev2) Patchwork

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