From: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: ville.syrjala@intel.com
Subject: [Intel-gfx] [RFC 4/4] drm/i915: Apply CDCLK quirk only on QS parts
Date: Mon, 2 Jan 2023 11:50:05 +0530 [thread overview]
Message-ID: <20230102062005.720964-5-chaitanya.kumar.borah@intel.com> (raw)
In-Reply-To: <20230102062005.720964-1-chaitanya.kumar.borah@intel.com>
RPL-U boards with ES silicon does not support the 480Mhz step of
CDCLK. To differentiate between QS and ES part CPU brand string
is the only feasible way as of now. ES parts have "Genuine Intel"
in their brand string while QS parts have a more specific brand
string, for ex. "13th Gen Intel(R) Core(TM) i5-1345U"
BSpec: 55409
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
---
drivers/gpu/drm/i915/display/intel_quirks.c | 32 +++++++++++++++++++--
1 file changed, 29 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_quirks.c b/drivers/gpu/drm/i915/display/intel_quirks.c
index 0a30499835b3..a6d7a2430626 100644
--- a/drivers/gpu/drm/i915/display/intel_quirks.c
+++ b/drivers/gpu/drm/i915/display/intel_quirks.c
@@ -14,6 +14,25 @@ static void intel_set_quirk(struct drm_i915_private *i915, enum intel_quirk_id q
i915->display.quirks.mask |= BIT(quirk);
}
+/*
+ * To differentiate between QS and ES part CPU brand string is the only feasible way
+ * as of now. ES parts have "Genuine Intel" in their brand string while QS parts have a more
+ * specific brand string, for ex. "13th Gen Intel(R) Core(TM) i5-1345U"
+ */
+static bool is_QS_part(void)
+{
+ struct cpuinfo_x86 *c;
+ unsigned int cpu = get_cpu();
+
+ c = &cpu_data(cpu);
+ put_cpu();
+
+ if (c->x86_model_id[0] && !strstr(c->x86_model_id, "Genuine Intel"))
+ return true;
+
+ return false;
+}
+
/*
* Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
*/
@@ -67,12 +86,19 @@ static void quirk_no_pps_backlight_power_hook(struct drm_i915_private *i915)
/*
* A new step of 480MHz has been added on SKUs that have a RPL-U device id.
- * This particular step is to better support 120Hz panels.
+ * This particular step is to better support 120Hz panels. In addition to
+ * identifying RPL-U device id, we need to make a distinction between ES and
+ * QS parts as this change comes only to QS parts. For this CPUID Brand
+ * string is used. 480Mhz step is only supported in SKUs which does not
+ * contain the string "Genuine Intel" in the Brand string.
*/
+
static void quirk_480mhz_cdclk_step_hook(struct drm_i915_private *i915)
{
- intel_set_quirk(i915, QUIRK_480MHZ_CDCLK_STEP);
- drm_info(&i915->drm, "Applying 480MHz CDCLK step quirk\n");
+ if (is_QS_part()) {
+ intel_set_quirk(i915, QUIRK_480MHZ_CDCLK_STEP);
+ drm_info(&i915->drm, "Applying 480MHz CDCLK step quirk\n");
+ }
}
struct intel_quirk {
--
2.25.1
next prev parent reply other threads:[~2023-01-02 6:20 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-02 6:20 [Intel-gfx] [RFC 0/4] Add new CDCLK step for RPL-U Chaitanya Kumar Borah
2023-01-02 6:20 ` [Intel-gfx] [RFC 1/4] drm/i915/quirks: Add quirk for 480MHz CDCLK step Chaitanya Kumar Borah
2023-01-02 10:03 ` Jani Nikula
2023-01-02 10:39 ` Jani Nikula
2023-01-07 5:52 ` Borah, Chaitanya Kumar
2023-01-02 6:20 ` [Intel-gfx] [RFC 2/4] drm/i915/display: Add 480 MHz CDCLK steps for RPL-U Chaitanya Kumar Borah
2023-01-02 10:05 ` Jani Nikula
2023-01-02 6:20 ` [Intel-gfx] [RFC 3/4] drm/i915: Initialize intel quirks before CDCLK initialization Chaitanya Kumar Borah
2023-01-02 10:07 ` Jani Nikula
2023-01-02 6:20 ` Chaitanya Kumar Borah [this message]
2023-01-02 10:03 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for Add new CDCLK step for RPL-U (rev2) Patchwork
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