From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 6/6] drm/i915: Move PLANE_BUG_CFG bit definitons to the correct place
Date: Mon, 20 Mar 2023 11:05:22 +0200 [thread overview]
Message-ID: <20230320090522.9909-7-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20230320090522.9909-1-ville.syrjala@linux.intel.com>
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
All other skl+ universal plane register bit definitons are next
to the pipe A register definition. Move the PLANE_BUF_CFG bit
definitions there as well.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 09849bcb1ccf..f79e8a544f51 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4649,6 +4649,11 @@
#define PLANE_CHICKEN_DISABLE_DPT REG_BIT(19) /* mtl+ */
#define _PLANE_BUF_CFG_1_A 0x7027c
#define _PLANE_BUF_CFG_2_A 0x7037c
+/* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */
+#define PLANE_BUF_END_MASK REG_GENMASK(27, 16)
+#define PLANE_BUF_END(end) REG_FIELD_PREP(PLANE_BUF_END_MASK, (end))
+#define PLANE_BUF_START_MASK REG_GENMASK(11, 0)
+#define PLANE_BUF_START(start) REG_FIELD_PREP(PLANE_BUF_START_MASK, (start))
#define _PLANE_NV12_BUF_CFG_1_A 0x70278
#define _PLANE_NV12_BUF_CFG_2_A 0x70378
@@ -4801,11 +4806,6 @@
#define _PLANE_BUF_CFG_1_B 0x7127c
#define _PLANE_BUF_CFG_2_B 0x7137c
-/* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */
-#define PLANE_BUF_END_MASK REG_GENMASK(27, 16)
-#define PLANE_BUF_END(end) REG_FIELD_PREP(PLANE_BUF_END_MASK, (end))
-#define PLANE_BUF_START_MASK REG_GENMASK(11, 0)
-#define PLANE_BUF_START(start) REG_FIELD_PREP(PLANE_BUF_START_MASK, (start))
#define _PLANE_BUF_CFG_1(pipe) \
_PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B)
#define _PLANE_BUF_CFG_2(pipe) \
--
2.39.2
next prev parent reply other threads:[~2023-03-20 9:05 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-20 9:05 [Intel-gfx] [PATCH 0/6] drm/i915/dpt: Fix DPT+shmem combo and add i915.enable_dpt modparam Ville Syrjala
2023-03-20 9:05 ` [Intel-gfx] [PATCH 1/6] drm/i915/dpt: Treat the DPT BO as a framebuffer Ville Syrjala
2023-03-20 9:46 ` Matthew Auld
2023-03-20 9:05 ` [Intel-gfx] [PATCH 2/6] drm/i915/dpt: Only do the POT stride remap when using DPT Ville Syrjala
2023-03-20 9:05 ` [Intel-gfx] [PATCH 3/6] drm/i915/dpt: Introduce HAS_DPT() Ville Syrjala
2023-03-20 9:05 ` [Intel-gfx] [PATCH 4/6] drm/i915: Add PLANE_CHICKEN registers Ville Syrjala
2023-03-20 9:05 ` [Intel-gfx] [PATCH 5/6] drm/i915/dpt: Add a modparam to disable DPT via the chicken bit Ville Syrjala
2023-03-20 9:05 ` Ville Syrjala [this message]
2023-03-20 16:17 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dpt: Fix DPT+shmem combo and add i915.enable_dpt modparam Patchwork
2023-03-20 16:17 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-03-20 16:17 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
2023-03-20 16:25 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-03-20 20:04 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2023-03-22 15:15 ` [Intel-gfx] [PATCH 0/6] " Juha-Pekka Heikkila
2023-03-22 16:15 ` Ville Syrjälä
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