From: "Jouni Högander" <jouni.hogander@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v7 2/6] drm/i915/psr: Modify/Fix Wa_16013835468 and prepare for Wa_14015648006
Date: Wed, 29 Mar 2023 18:06:59 +0300 [thread overview]
Message-ID: <20230329150703.432072-3-jouni.hogander@intel.com> (raw)
In-Reply-To: <20230329150703.432072-1-jouni.hogander@intel.com>
Wa_16013835468 is a separate from Wa_14015648006 and needs to be
applied for display version 12. Fix this by removing all the
references to Wa_14015648006 and apply Wa_16013835468 according to
Bspec.
Also move workaround into separate function as a preparation for
Wa_14015648006 implementation.
Bspec: 55378
v3:
- apply for display version 12 only
v2:
- keep applying the wa in intel_psr_enable_source
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
drivers/gpu/drm/i915/display/intel_psr.c | 35 ++++++++++++++++--------
1 file changed, 24 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 8dbf452d63c2..770f6fea5499 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1134,6 +1134,28 @@ static u32 wa_16013835468_bit_get(struct intel_dp *intel_dp)
}
}
+/*
+ * Wa_16013835468
+ */
+static void wm_optimization_wa(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ bool set_wa_bit = false;
+
+ /* Wa_16013835468 */
+ if (DISPLAY_VER(dev_priv) == 12)
+ set_wa_bit |= crtc_state->hw.adjusted_mode.crtc_vblank_start !=
+ crtc_state->hw.adjusted_mode.crtc_vdisplay;
+
+ if (set_wa_bit)
+ intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1,
+ 0, wa_16013835468_bit_get(intel_dp));
+ else
+ intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1,
+ wa_16013835468_bit_get(intel_dp), 0);
+}
+
static void intel_psr_enable_source(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state)
{
@@ -1175,15 +1197,8 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
/*
* Wa_16013835468
- * Wa_14015648006
*/
- if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
- IS_DISPLAY_VER(dev_priv, 12, 13)) {
- if (crtc_state->hw.adjusted_mode.crtc_vblank_start !=
- crtc_state->hw.adjusted_mode.crtc_vdisplay)
- intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, 0,
- wa_16013835468_bit_get(intel_dp));
- }
+ wm_optimization_wa(intel_dp, crtc_state);
if (intel_dp->psr.psr2_enabled) {
if (DISPLAY_VER(dev_priv) == 9)
@@ -1359,10 +1374,8 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
/*
* Wa_16013835468
- * Wa_14015648006
*/
- if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
- IS_DISPLAY_VER(dev_priv, 12, 13))
+ if (DISPLAY_VER(dev_priv) == 12)
intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1,
wa_16013835468_bit_get(intel_dp), 0);
--
2.34.1
next prev parent reply other threads:[~2023-03-29 15:11 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-29 15:06 [Intel-gfx] [PATCH v7 0/6] High refresh rate PSR fixes Jouni Högander
2023-03-29 15:06 ` [Intel-gfx] [PATCH v7 1/6] drm/i915/psr: Unify pre/post hooks Jouni Högander
2023-03-29 15:06 ` Jouni Högander [this message]
2023-03-29 15:07 ` [Intel-gfx] [PATCH v7 3/6] drm/i915/psr: Implement Wa_14015648006 Jouni Högander
2023-03-29 15:07 ` [Intel-gfx] [PATCH v7 4/6] drm/i915/psr: Add helpers for block count number handling Jouni Högander
2023-03-29 15:07 ` [Intel-gfx] [PATCH v7 5/6] drm/i915/psr: Check that vblank is long enough for psr2 Jouni Högander
2023-03-29 15:07 ` [Intel-gfx] [PATCH v7 6/6] drm/i915/psr: Implement Display WA #1136 Jouni Högander
2023-03-29 19:21 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for High refresh rate PSR fixes (rev7) Patchwork
2023-03-29 19:31 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-03-30 11:59 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2023-03-30 12:23 ` [Intel-gfx] [PATCH v7 0/6] High refresh rate PSR fixes Ville Syrjälä
2023-03-31 5:55 ` Hogander, Jouni
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