From: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
Subject: [Intel-gfx] [PATCH 01/11] drm/i915/skl: s/SKL/SKYLAKE for platform/subplatform defines
Date: Fri, 16 Jun 2023 17:11:50 +0530 [thread overview]
Message-ID: <20230616114200.3228284-2-dnyaneshwar.bhadane@intel.com> (raw)
In-Reply-To: <20230616114200.3228284-1-dnyaneshwar.bhadane@intel.com>
Follow consistent naming convention. Replace SKL with
SKYLAKE.
Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c | 4 ++--
drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 14 +++++++-------
3 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
index b7d20485bde5..13a2c364b8eb 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
@@ -1724,9 +1724,9 @@ void intel_ddi_buf_trans_init(struct intel_encoder *encoder)
encoder->get_buf_trans = kbl_u_get_buf_trans;
} else if (IS_COMETLAKE(i915) || IS_COFFEELAKE(i915) || IS_KABYLAKE(i915)) {
encoder->get_buf_trans = kbl_get_buf_trans;
- } else if (IS_SKL_ULX(i915)) {
+ } else if (IS_SKYLAKE_ULX(i915)) {
encoder->get_buf_trans = skl_y_get_buf_trans;
- } else if (IS_SKL_ULT(i915)) {
+ } else if (IS_SKYLAKE_ULT(i915)) {
encoder->get_buf_trans = skl_u_get_buf_trans;
} else if (IS_SKYLAKE(i915)) {
encoder->get_buf_trans = skl_get_buf_trans;
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 4d2dece96011..38ecbe793ea4 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1173,7 +1173,7 @@ skl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
/* WaInPlaceDecompressionHang:skl */
- if (IS_SKL_GRAPHICS_STEP(gt->i915, STEP_A0, STEP_H0))
+ if (IS_SKYLAKE_GRAPHICS_STEP(gt->i915, STEP_A0, STEP_H0))
wa_write_or(wal,
GEN9_GAMT_ECO_REG_RW_IA,
GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b4cf6f0f636d..71dd1d80dc97 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -610,19 +610,19 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
/* ULX machines are also considered ULT. */
#define IS_HSW_ULX(i915) \
IS_SUBPLATFORM(i915, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
-#define IS_SKL_ULT(i915) \
+#define IS_SKYLAKE_ULT(i915) \
IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
-#define IS_SKL_ULX(i915) \
+#define IS_SKYLAKE_ULX(i915) \
IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
#define IS_KBL_ULT(i915) \
IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
#define IS_KBL_ULX(i915) \
IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
-#define IS_SKL_GT2(i915) (IS_SKYLAKE(i915) && \
+#define IS_SKYLAKE_GT2(i915) (IS_SKYLAKE(i915) && \
INTEL_INFO(i915)->gt == 2)
-#define IS_SKL_GT3(i915) (IS_SKYLAKE(i915) && \
+#define IS_SKYLAKE_GT3(i915) (IS_SKYLAKE(i915) && \
INTEL_INFO(i915)->gt == 3)
-#define IS_SKL_GT4(i915) (IS_SKYLAKE(i915) && \
+#define IS_SKYLAKE_GT4(i915) (IS_SKYLAKE(i915) && \
INTEL_INFO(i915)->gt == 4)
#define IS_KBL_GT2(i915) (IS_KABYLAKE(i915) && \
INTEL_INFO(i915)->gt == 2)
@@ -650,7 +650,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define IS_TGL_UY(i915) \
IS_SUBPLATFORM(i915, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_UY)
-#define IS_SKL_GRAPHICS_STEP(p, since, until) (IS_SKYLAKE(p) && IS_GRAPHICS_STEP(p, since, until))
+#define IS_SKYLAKE_GRAPHICS_STEP(p, since, until) (IS_SKYLAKE(p) && IS_GRAPHICS_STEP(p, since, until))
#define IS_KBL_GRAPHICS_STEP(i915, since, until) \
(IS_KABYLAKE(i915) && IS_GRAPHICS_STEP(i915, since, until))
@@ -801,7 +801,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
/* WaRsDisableCoarsePowerGating:skl,cnl */
#define NEEDS_WaRsDisableCoarsePowerGating(i915) \
- (IS_SKL_GT3(i915) || IS_SKL_GT4(i915))
+ (IS_SKYLAKE_GT3(i915) || IS_SKYLAKE_GT4(i915))
/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
* rows, which changed the alignment requirements and fence programming.
--
2.34.1
next prev parent reply other threads:[~2023-06-16 11:42 UTC|newest]
Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-15 9:54 [Intel-gfx] [PATCH 00/11] Replace acronym with full platform name in defines Dnyaneshwar Bhadane
2023-06-15 9:54 ` [Intel-gfx] [PATCH 01/11] drm/i915/TGL: s/TGL/TIGERLAKE for platform/subplatform defines Dnyaneshwar Bhadane
2023-06-15 9:54 ` [Intel-gfx] [PATCH 02/11] drm/i915/MTL: s/MTL/METEORLAKE " Dnyaneshwar Bhadane
2023-06-15 9:54 ` [Intel-gfx] [PATCH 03/11] drm/i915/TGL: s/RKL/ROCKETLAKE " Dnyaneshwar Bhadane
2023-06-15 9:54 ` [Intel-gfx] [PATCH 04/11] drm/i915/JSL: s/JSL/JASPERLAKE " Dnyaneshwar Bhadane
2023-06-19 8:46 ` Jani Nikula
2023-06-20 14:36 ` Srivatsa, Anusha
2023-06-15 9:54 ` [Intel-gfx] [PATCH 05/11] drm/i915/KBL: s/KBL/KABYLAKE " Dnyaneshwar Bhadane
2023-06-15 9:54 ` [Intel-gfx] [PATCH 06/11] drm/i915/SKL: s/SKL/SKYLAKE " Dnyaneshwar Bhadane
2023-06-15 9:54 ` [Intel-gfx] [PATCH 07/11] drm/i915/adlp: s/ADLP/ALDERLAKE_P for display and graphics step Dnyaneshwar Bhadane
2023-06-15 9:54 ` [Intel-gfx] [PATCH 08/11] drm/i915/rplp: s/ADLP/ALDERLAKE_P for RPLP defines Dnyaneshwar Bhadane
2023-06-15 9:54 ` [Intel-gfx] [PATCH 09/11] drm/i915/adln: s/ADLP/ALDERLAKE_P in ADLN defines Dnyaneshwar Bhadane
2023-06-15 9:54 ` [Intel-gfx] [PATCH 10/11] drm/i915/adls: s/ADLS/ALDERLAKE_S in platform and subplatform defines Dnyaneshwar Bhadane
2023-06-15 21:51 ` Srivatsa, Anusha
2023-06-15 9:54 ` [Intel-gfx] [PATCH 11/11] drm/i915/rplu: s/ADLP/ALDERLAKE_P in RPLU defines Dnyaneshwar Bhadane
2023-06-15 18:26 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Replace acronym with full platform name in defines Patchwork
2023-06-15 18:26 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-06-15 18:36 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-06-16 0:13 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2023-06-16 11:41 ` [Intel-gfx] [PATCH 00/11] " Dnyaneshwar Bhadane
2023-06-16 11:41 ` Dnyaneshwar Bhadane [this message]
2023-06-16 11:41 ` [Intel-gfx] [PATCH 02/11] drm/i915/kbl: s/KBL/KABYLAKE for platform/subplatform defines Dnyaneshwar Bhadane
2023-06-16 11:41 ` [Intel-gfx] [PATCH 03/11] drm/i915/tgl: s/RKL/ROCKETLAKE " Dnyaneshwar Bhadane
2023-06-16 11:41 ` [Intel-gfx] [PATCH 04/11] drm/i915/jsl: s/JSL/JASPERLAKE " Dnyaneshwar Bhadane
2023-06-16 11:41 ` [Intel-gfx] [PATCH 05/11] drm/i915/tgl: s/TGL/TIGERLAKE " Dnyaneshwar Bhadane
2023-06-16 11:41 ` [Intel-gfx] [PATCH 06/11] drm/i915/adlp: s/ADLP/ALDERLAKE_P for display and graphics step Dnyaneshwar Bhadane
2023-06-16 11:41 ` [Intel-gfx] [PATCH 07/11] drm/i915/rplp: s/ADLP/ALDERLAKE_P for RPLP defines Dnyaneshwar Bhadane
2023-06-16 11:41 ` [Intel-gfx] [PATCH 08/11] drm/i915/rplu: s/ADLP/ALDERLAKE_P in RPLU defines Dnyaneshwar Bhadane
2023-06-16 11:41 ` [Intel-gfx] [PATCH 09/11] drm/i915/adln: s/ADLP/ALDERLAKE_P in ADLN defines Dnyaneshwar Bhadane
2023-06-16 11:41 ` [Intel-gfx] [PATCH 10/11] drm/i915/adls: s/ADLS/ALDERLAKE_S in platform and subplatform defines Dnyaneshwar Bhadane
2023-06-16 11:42 ` [Intel-gfx] [PATCH 11/11] drm/i915/mtl: s/MTL/METEORLAKE for platform/subplatform defines Dnyaneshwar Bhadane
2023-06-16 12:05 ` Tvrtko Ursulin
2023-06-16 12:07 ` Tvrtko Ursulin
2023-06-22 17:42 ` Bhadane, Dnyaneshwar
2023-06-21 21:11 ` Matt Roper
2023-06-22 9:38 ` Tvrtko Ursulin
2023-06-30 11:40 ` [Intel-gfx] [v2] " Dnyaneshwar Bhadane
2023-07-06 17:45 ` Srivatsa, Anusha
2023-07-10 10:58 ` [Intel-gfx] [v3] " Dnyaneshwar Bhadane
2023-07-10 13:44 ` Bhadane, Dnyaneshwar
2023-07-12 17:20 ` Srivatsa, Anusha
2023-07-13 8:38 ` Tvrtko Ursulin
2023-07-13 9:39 ` Jani Nikula
2023-07-13 11:56 ` Tvrtko Ursulin
2023-07-13 12:12 ` Bhadane, Dnyaneshwar
2023-07-13 12:24 ` Tvrtko Ursulin
2023-07-13 12:43 ` Bhadane, Dnyaneshwar
2023-07-13 12:55 ` Jani Nikula
2023-07-13 12:57 ` Jani Nikula
2023-07-17 6:42 ` Bhadane, Dnyaneshwar
2023-07-17 11:00 ` Tvrtko Ursulin
2023-06-20 16:30 ` [Intel-gfx] [PATCH 00/11] Replace acronym with full platform name in defines Jani Nikula
2023-06-21 10:30 ` Tvrtko Ursulin
2023-06-21 11:25 ` Jani Nikula
2023-06-21 17:30 ` Srivatsa, Anusha
2023-07-10 13:45 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Replace acronym with full platform name in defines. (rev3) Patchwork
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