From: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
Subject: [Intel-gfx] [PATCH 05/11] drm/i915/tgl: s/TGL/TIGERLAKE for platform/subplatform defines
Date: Fri, 16 Jun 2023 17:11:54 +0530 [thread overview]
Message-ID: <20230616114200.3228284-6-dnyaneshwar.bhadane@intel.com> (raw)
In-Reply-To: <20230616114200.3228284-1-dnyaneshwar.bhadane@intel.com>
Follow consistent naming convention. Replace TGL with
TIGERLAKE.
Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c | 2 +-
drivers/gpu/drm/i915/display/skl_universal_plane.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 4 ++--
drivers/gpu/drm/i915/intel_step.c | 2 +-
4 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
index cd6915e9e138..ab84d003232c 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
@@ -1390,7 +1390,7 @@ tgl_get_combo_buf_trans_dp(struct intel_encoder *encoder,
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
if (crtc_state->port_clock > 270000) {
- if (IS_TGL_UY(dev_priv)) {
+ if (IS_TIGERLAKE_UY(dev_priv)) {
return intel_get_buf_trans(&tgl_uy_combo_phy_trans_dp_hbr2,
n_entries);
} else {
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 6b01a0b68b97..26def9cb86e4 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -2196,7 +2196,7 @@ static bool gen12_plane_has_mc_ccs(struct drm_i915_private *i915,
/* Wa_14010477008 */
if (IS_DG1(i915) || IS_ROCKETLAKE(i915) ||
- IS_TGL_DISPLAY_STEP(i915, STEP_A0, STEP_D0))
+ IS_TIGERLAKE_DISPLAY_STEP(i915, STEP_A0, STEP_D0))
return false;
/* Wa_22011186057 */
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b6a720ac48bf..865977d69f7e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -647,7 +647,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define IS_ICL_WITH_PORT_F(i915) \
IS_SUBPLATFORM(i915, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
-#define IS_TGL_UY(i915) \
+#define IS_TIGERLAKE_UY(i915) \
IS_SUBPLATFORM(i915, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_UY)
#define IS_SKYLAKE_GRAPHICS_STEP(p, since, until) (IS_SKYLAKE(p) && IS_GRAPHICS_STEP(p, since, until))
@@ -662,7 +662,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define IS_JASPERLAKE_EHL_DISPLAY_STEP(p, since, until) \
(IS_JASPERLAKE_EHL(p) && IS_DISPLAY_STEP(p, since, until))
-#define IS_TGL_DISPLAY_STEP(__i915, since, until) \
+#define IS_TIGERLAKE_DISPLAY_STEP(__i915, since, until) \
(IS_TIGERLAKE(__i915) && \
IS_DISPLAY_STEP(__i915, since, until))
diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c
index 3469d912e83e..847c7de50e1f 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -213,7 +213,7 @@ void intel_step_init(struct drm_i915_private *i915)
} else if (IS_ROCKETLAKE(i915)) {
revids = rkl_revids;
size = ARRAY_SIZE(rkl_revids);
- } else if (IS_TGL_UY(i915)) {
+ } else if (IS_TIGERLAKE_UY(i915)) {
revids = tgl_uy_revids;
size = ARRAY_SIZE(tgl_uy_revids);
} else if (IS_TIGERLAKE(i915)) {
--
2.34.1
next prev parent reply other threads:[~2023-06-16 11:42 UTC|newest]
Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-15 9:54 [Intel-gfx] [PATCH 00/11] Replace acronym with full platform name in defines Dnyaneshwar Bhadane
2023-06-15 9:54 ` [Intel-gfx] [PATCH 01/11] drm/i915/TGL: s/TGL/TIGERLAKE for platform/subplatform defines Dnyaneshwar Bhadane
2023-06-15 9:54 ` [Intel-gfx] [PATCH 02/11] drm/i915/MTL: s/MTL/METEORLAKE " Dnyaneshwar Bhadane
2023-06-15 9:54 ` [Intel-gfx] [PATCH 03/11] drm/i915/TGL: s/RKL/ROCKETLAKE " Dnyaneshwar Bhadane
2023-06-15 9:54 ` [Intel-gfx] [PATCH 04/11] drm/i915/JSL: s/JSL/JASPERLAKE " Dnyaneshwar Bhadane
2023-06-19 8:46 ` Jani Nikula
2023-06-20 14:36 ` Srivatsa, Anusha
2023-06-15 9:54 ` [Intel-gfx] [PATCH 05/11] drm/i915/KBL: s/KBL/KABYLAKE " Dnyaneshwar Bhadane
2023-06-15 9:54 ` [Intel-gfx] [PATCH 06/11] drm/i915/SKL: s/SKL/SKYLAKE " Dnyaneshwar Bhadane
2023-06-15 9:54 ` [Intel-gfx] [PATCH 07/11] drm/i915/adlp: s/ADLP/ALDERLAKE_P for display and graphics step Dnyaneshwar Bhadane
2023-06-15 9:54 ` [Intel-gfx] [PATCH 08/11] drm/i915/rplp: s/ADLP/ALDERLAKE_P for RPLP defines Dnyaneshwar Bhadane
2023-06-15 9:54 ` [Intel-gfx] [PATCH 09/11] drm/i915/adln: s/ADLP/ALDERLAKE_P in ADLN defines Dnyaneshwar Bhadane
2023-06-15 9:54 ` [Intel-gfx] [PATCH 10/11] drm/i915/adls: s/ADLS/ALDERLAKE_S in platform and subplatform defines Dnyaneshwar Bhadane
2023-06-15 21:51 ` Srivatsa, Anusha
2023-06-15 9:54 ` [Intel-gfx] [PATCH 11/11] drm/i915/rplu: s/ADLP/ALDERLAKE_P in RPLU defines Dnyaneshwar Bhadane
2023-06-15 18:26 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Replace acronym with full platform name in defines Patchwork
2023-06-15 18:26 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-06-15 18:36 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-06-16 0:13 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2023-06-16 11:41 ` [Intel-gfx] [PATCH 00/11] " Dnyaneshwar Bhadane
2023-06-16 11:41 ` [Intel-gfx] [PATCH 01/11] drm/i915/skl: s/SKL/SKYLAKE for platform/subplatform defines Dnyaneshwar Bhadane
2023-06-16 11:41 ` [Intel-gfx] [PATCH 02/11] drm/i915/kbl: s/KBL/KABYLAKE " Dnyaneshwar Bhadane
2023-06-16 11:41 ` [Intel-gfx] [PATCH 03/11] drm/i915/tgl: s/RKL/ROCKETLAKE " Dnyaneshwar Bhadane
2023-06-16 11:41 ` [Intel-gfx] [PATCH 04/11] drm/i915/jsl: s/JSL/JASPERLAKE " Dnyaneshwar Bhadane
2023-06-16 11:41 ` Dnyaneshwar Bhadane [this message]
2023-06-16 11:41 ` [Intel-gfx] [PATCH 06/11] drm/i915/adlp: s/ADLP/ALDERLAKE_P for display and graphics step Dnyaneshwar Bhadane
2023-06-16 11:41 ` [Intel-gfx] [PATCH 07/11] drm/i915/rplp: s/ADLP/ALDERLAKE_P for RPLP defines Dnyaneshwar Bhadane
2023-06-16 11:41 ` [Intel-gfx] [PATCH 08/11] drm/i915/rplu: s/ADLP/ALDERLAKE_P in RPLU defines Dnyaneshwar Bhadane
2023-06-16 11:41 ` [Intel-gfx] [PATCH 09/11] drm/i915/adln: s/ADLP/ALDERLAKE_P in ADLN defines Dnyaneshwar Bhadane
2023-06-16 11:41 ` [Intel-gfx] [PATCH 10/11] drm/i915/adls: s/ADLS/ALDERLAKE_S in platform and subplatform defines Dnyaneshwar Bhadane
2023-06-16 11:42 ` [Intel-gfx] [PATCH 11/11] drm/i915/mtl: s/MTL/METEORLAKE for platform/subplatform defines Dnyaneshwar Bhadane
2023-06-16 12:05 ` Tvrtko Ursulin
2023-06-16 12:07 ` Tvrtko Ursulin
2023-06-22 17:42 ` Bhadane, Dnyaneshwar
2023-06-21 21:11 ` Matt Roper
2023-06-22 9:38 ` Tvrtko Ursulin
2023-06-30 11:40 ` [Intel-gfx] [v2] " Dnyaneshwar Bhadane
2023-07-06 17:45 ` Srivatsa, Anusha
2023-07-10 10:58 ` [Intel-gfx] [v3] " Dnyaneshwar Bhadane
2023-07-10 13:44 ` Bhadane, Dnyaneshwar
2023-07-12 17:20 ` Srivatsa, Anusha
2023-07-13 8:38 ` Tvrtko Ursulin
2023-07-13 9:39 ` Jani Nikula
2023-07-13 11:56 ` Tvrtko Ursulin
2023-07-13 12:12 ` Bhadane, Dnyaneshwar
2023-07-13 12:24 ` Tvrtko Ursulin
2023-07-13 12:43 ` Bhadane, Dnyaneshwar
2023-07-13 12:55 ` Jani Nikula
2023-07-13 12:57 ` Jani Nikula
2023-07-17 6:42 ` Bhadane, Dnyaneshwar
2023-07-17 11:00 ` Tvrtko Ursulin
2023-06-20 16:30 ` [Intel-gfx] [PATCH 00/11] Replace acronym with full platform name in defines Jani Nikula
2023-06-21 10:30 ` Tvrtko Ursulin
2023-06-21 11:25 ` Jani Nikula
2023-06-21 17:30 ` Srivatsa, Anusha
2023-07-10 13:45 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Replace acronym with full platform name in defines. (rev3) Patchwork
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