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From: Andi Shyti <andi.shyti@linux.intel.com>
To: Jonathan Cavitt <jonathan.cavitt@intel.com>,
	Matt Roper <matthew.d.roper@intel.com>,
	Chris Wilson <chris@chris-wilson.co.uk>,
	Mika Kuoppala <mika.kuoppala@linux.intel.com>,
	Nirmoy Das <nirmoy.das@intel.com>
Cc: Intel GFX <intel-gfx@lists.freedesktop.org>,
	DRI Devel <dri-devel@lists.freedesktop.org>
Subject: [Intel-gfx] [PATCH v4 2/6] drm/i915/gt: Ensure memory quiesced before invalidation
Date: Mon, 17 Jul 2023 19:30:55 +0200	[thread overview]
Message-ID: <20230717173059.422892-3-andi.shyti@linux.intel.com> (raw)
In-Reply-To: <20230717173059.422892-1-andi.shyti@linux.intel.com>

From: Jonathan Cavitt <jonathan.cavitt@intel.com>

All memory traffic must be quiesced before requesting
an aux invalidation on platforms that use Aux CCS.

Fixes: 972282c4cf24 ("drm/i915/gen12: Add aux table invalidate for all engines")
Signed-off-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
Cc: <stable@vger.kernel.org> # v5.8+
---
 drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index 563efee055602..bee3b7dc595cf 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -202,6 +202,13 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
 {
 	struct intel_engine_cs *engine = rq->engine;
 
+	/*
+	 * Aux invalidations on Aux CCS platforms require
+	 * memory traffic is quiesced prior.
+	 */
+	if ((mode & EMIT_INVALIDATE) && !HAS_FLAT_CCS(engine->i915))
+		mode |= EMIT_FLUSH;
+
 	if (mode & EMIT_FLUSH) {
 		u32 flags = 0;
 		int err;
-- 
2.40.1


  parent reply	other threads:[~2023-07-17 17:31 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-07-17 17:30 [Intel-gfx] [PATCH v4 0/6] Update AUX invalidation sequence Andi Shyti
2023-07-17 17:30 ` [Intel-gfx] [PATCH v4 1/6] drm/i915/gt: Cleanup aux invalidation registers Andi Shyti
2023-07-17 17:30 ` Andi Shyti [this message]
2023-07-17 17:54   ` [Intel-gfx] [PATCH v4 2/6] drm/i915/gt: Ensure memory quiesced before invalidation Matt Roper
2023-07-17 20:31     ` Matt Roper
2023-07-17 21:52       ` Andi Shyti
2023-07-17 22:00         ` Matt Roper
2023-07-18  0:28           ` Andi Shyti
2023-07-18 15:53             ` Matt Roper
2023-07-17 17:30 ` [Intel-gfx] [PATCH v4 3/6] drm/i915/gt: Rename flags with bit_group_X according to the datasheet Andi Shyti
2023-07-17 17:32   ` Andi Shyti
2023-07-17 17:59   ` Matt Roper
2023-07-17 18:21   ` Andrzej Hajda
2023-07-17 21:54     ` Andi Shyti
2023-07-17 18:45   ` Nirmoy Das
2023-07-17 17:30 ` [Intel-gfx] [PATCH v4 4/6] drm/i915/gt: Enable the CCS_FLUSH bit in the pipe control Andi Shyti
2023-07-17 18:23   ` Andrzej Hajda
2023-07-17 19:40   ` Matt Roper
2023-07-17 17:30 ` [Intel-gfx] [PATCH v4 5/6] drm/i915/gt: Poll aux invalidation register bit on invalidation Andi Shyti
2023-07-17 18:51   ` Andrzej Hajda
2023-07-17 20:05   ` Matt Roper
2023-07-17 17:30 ` [Intel-gfx] [PATCH v4 6/6] drm/i915/gt: Support aux invalidation on all engines Andi Shyti
2023-07-17 19:11   ` Andrzej Hajda
2023-07-17 22:00     ` Andi Shyti
2023-07-17 20:27   ` Matt Roper
2023-07-17 22:02     ` Andi Shyti
2023-07-17 21:07 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Update AUX invalidation sequence (rev4) Patchwork
2023-07-17 21:07 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-07-17 21:26 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-07-18  3:06 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork

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