From: Andi Shyti <andi.shyti@linux.intel.com>
To: Andrzej Hajda <andrzej.hajda@intel.com>
Cc: Intel GFX <intel-gfx@lists.freedesktop.org>,
Jonathan Cavitt <jonathan.cavitt@intel.com>,
DRI Devel <dri-devel@lists.freedesktop.org>,
Chris Wilson <chris@chris-wilson.co.uk>,
Matt Roper <matthew.d.roper@intel.com>,
Nirmoy Das <nirmoy.das@intel.com>
Subject: Re: [Intel-gfx] [PATCH v4 6/6] drm/i915/gt: Support aux invalidation on all engines
Date: Tue, 18 Jul 2023 00:00:01 +0200 [thread overview]
Message-ID: <ZLW54d83qzX40XNT@ashyti-mobl2.lan> (raw)
In-Reply-To: <58136997-4870-c321-a04a-d10443e92546@intel.com>
Hi Andrzej,
On Mon, Jul 17, 2023 at 09:11:26PM +0200, Andrzej Hajda wrote:
> On 17.07.2023 19:30, Andi Shyti wrote:
> > Perform some refactoring with the purpose of keeping in one
> > single place all the operations around the aux table
> > invalidation.
> >
> > With this refactoring add more engines where the invalidation
> > should be performed.
> >
> > Fixes: 972282c4cf24 ("drm/i915/gen12: Add aux table invalidate for all engines")
> > Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
> > Cc: <stable@vger.kernel.org> # v5.8+
> > ---
> > drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 63 +++++++++++++++---------
> > drivers/gpu/drm/i915/gt/gen8_engine_cs.h | 3 +-
> > drivers/gpu/drm/i915/gt/intel_lrc.c | 17 +------
> > 3 files changed, 44 insertions(+), 39 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> > index fbc70f3b7f2fd..6d21a1ac06e73 100644
> > --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> > +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> > @@ -165,7 +165,8 @@ static u32 preparser_disable(bool state)
> > return MI_ARB_CHECK | 1 << 8 | state;
> > }
> > -u32 *gen12_emit_aux_table_inv(struct intel_gt *gt, u32 *cs, const i915_reg_t inv_reg)
> > +static u32 *gen12_emit_aux_table_inv(struct intel_gt *gt, u32 *cs,
> > + const i915_reg_t inv_reg)
> > {
> > u32 gsi_offset = gt->uncore->gsi_offset;
> > @@ -187,6 +188,40 @@ u32 *gen12_emit_aux_table_inv(struct intel_gt *gt, u32 *cs, const i915_reg_t inv
> > return cs;
> > }
> > +static i915_reg_t intel_get_aux_inv_reg(struct intel_engine_cs *engine)
> > +{
> > + if (HAS_FLAT_CCS(engine->i915))
> > + return _MMIO(0);
>
> Why not INVALID_MMIO_REG ? Here and below.
>
> > +
> > + switch (engine->id) {
> > + case RCS0:
> > + return GEN12_CCS_AUX_INV;
> > + case VCS0:
> > + return GEN12_VD0_AUX_INV;
> > + case VCS2:
> > + return GEN12_VD2_AUX_INV;
> > + case VECS0:
> > + return GEN12_VE0_AUX_INV;
> > + default:
> > + return _MMIO(0);
> > + }
> > +}
> > +
> > +static bool intel_engine_has_aux_inv(struct intel_engine_cs *engine)
> > +{
> > + i915_reg_t reg = intel_get_aux_inv_reg(engine);
> > +
> > + return !!reg.reg;
>
> return i915_mmio_reg_valid(intel_get_aux_inv_reg(engine));
>
> > +}
> > +
> > +u32 *intel_emit_aux_table_inv(struct intel_engine_cs *engine, u32 *cs)
> > +{
> > + i915_reg_t reg = intel_get_aux_inv_reg(engine);
> > + struct intel_gt *gt = engine->gt;
> > +
> > + return reg.reg ? gen12_emit_aux_table_inv(gt, cs, reg) : cs;
> > +}
> > +
>
> I am not sure about prefixes, IMHO gen12_ instead of intel_ is more adequate
> as this is only gen12 feature, works only on gen12, and is called from gen12
> context, up to you. In any case we can squash intel_emit_aux_table_inv and
> gen12_emit_aux_table_inv into one function, am I right?
you and Matt have made exactly the same comments... will fix
them, Thank you!
Andi
next prev parent reply other threads:[~2023-07-17 22:00 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-17 17:30 [Intel-gfx] [PATCH v4 0/6] Update AUX invalidation sequence Andi Shyti
2023-07-17 17:30 ` [Intel-gfx] [PATCH v4 1/6] drm/i915/gt: Cleanup aux invalidation registers Andi Shyti
2023-07-17 17:30 ` [Intel-gfx] [PATCH v4 2/6] drm/i915/gt: Ensure memory quiesced before invalidation Andi Shyti
2023-07-17 17:54 ` Matt Roper
2023-07-17 20:31 ` Matt Roper
2023-07-17 21:52 ` Andi Shyti
2023-07-17 22:00 ` Matt Roper
2023-07-18 0:28 ` Andi Shyti
2023-07-18 15:53 ` Matt Roper
2023-07-17 17:30 ` [Intel-gfx] [PATCH v4 3/6] drm/i915/gt: Rename flags with bit_group_X according to the datasheet Andi Shyti
2023-07-17 17:32 ` Andi Shyti
2023-07-17 17:59 ` Matt Roper
2023-07-17 18:21 ` Andrzej Hajda
2023-07-17 21:54 ` Andi Shyti
2023-07-17 18:45 ` Nirmoy Das
2023-07-17 17:30 ` [Intel-gfx] [PATCH v4 4/6] drm/i915/gt: Enable the CCS_FLUSH bit in the pipe control Andi Shyti
2023-07-17 18:23 ` Andrzej Hajda
2023-07-17 19:40 ` Matt Roper
2023-07-17 17:30 ` [Intel-gfx] [PATCH v4 5/6] drm/i915/gt: Poll aux invalidation register bit on invalidation Andi Shyti
2023-07-17 18:51 ` Andrzej Hajda
2023-07-17 20:05 ` Matt Roper
2023-07-17 17:30 ` [Intel-gfx] [PATCH v4 6/6] drm/i915/gt: Support aux invalidation on all engines Andi Shyti
2023-07-17 19:11 ` Andrzej Hajda
2023-07-17 22:00 ` Andi Shyti [this message]
2023-07-17 20:27 ` Matt Roper
2023-07-17 22:02 ` Andi Shyti
2023-07-17 21:07 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Update AUX invalidation sequence (rev4) Patchwork
2023-07-17 21:07 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-07-17 21:26 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-07-18 3:06 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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